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Message-ID: <a590f1c3-dc8b-ca12-9323-df195244a87f@linaro.org>
Date: Thu, 20 Jul 2023 09:54:53 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Tengfei Fan <quic_tengfan@...cinc.com>, andersson@...nel.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org
Cc: quic_tsoni@...cinc.com, quic_shashim@...cinc.com,
quic_kaushalk@...cinc.com, quic_tdas@...cinc.com,
quic_tingweiz@...cinc.com, quic_aiquny@...cinc.com,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI
On 19.07.2023 12:01, Tengfei Fan wrote:
> This add based DTSI for SM4450 SoC and includes base description of
> CPUs and interrupt-controller which helps to boot to shell with
> console on boards with this SoC.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@...cinc.com>
> ---
[...]
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/gpio/gpio.h>
Please sort them alphabetically
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
[...]
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
Please post dmesg | grep '\[', this is probably a standard ARM core.
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + #cooling-cells = <2>;
> + L2_0: l2-cache {
Missing a newline before subnodes
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
Ditto
> + compatible = "cache";
> + cache-level = <3>;
> + cache-unified;
> + };
> + };
> + };
[...]
> +
> + intc: interrupt-controller@...00000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + #redistributor-regions = <1>;
> + redistributor-stride = <0x0 0x20000>;
> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
> + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
Misasligned
also, please move reg and interrupts after compatible
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + timer@...20000 {
> + compatible = "arm,armv7-timer-mem";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0x20000000>;
> + reg = <0x0 0x17420000 0x0 0x1000>;
> + clock-frequency = <19200000>;
Drop clock-frequency
[...]
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
Misaligned
> + clock-frequency = <19200000>;
Drop
Konrad
> + };
> +};
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