| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <1689840545-5094-4-git-send-email-quic_rohiagar@quicinc.com>
Date: Thu, 20 Jul 2023 13:39:04 +0530
From: Rohit Agarwal <quic_rohiagar@...cinc.com>
To: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Rohit Agarwal <quic_rohiagar@...cinc.com>
Subject: [PATCH 3/4] arm64: dts: qcom: sm8450: Update the RPMHPD bindings entry
Update the RPMHPD bindings entry as per the new generic bindings defined
in rpmhpd.h for SM8450 SoC.
Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 37 ++++++++++++++++++------------------
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 5cd7296..6bd6a6c 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -1149,7 +1150,7 @@
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
- power-domains = <&rpmhpd SM8450_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
@@ -1312,7 +1313,7 @@
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
- power-domains = <&rpmhpd SM8450_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
@@ -2097,8 +2098,8 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd SM8450_LCX>,
- <&rpmhpd SM8450_LMX>;
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
@@ -2372,8 +2373,8 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd SM8450_LCX>,
- <&rpmhpd SM8450_LMX>;
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&adsp_mem>;
@@ -2477,8 +2478,8 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd SM8450_CX>,
- <&rpmhpd SM8450_MXC>;
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MXC>;
power-domain-names = "cx", "mxc";
memory-region = <&cdsp_mem>;
@@ -2584,8 +2585,8 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd SM8450_CX>,
- <&rpmhpd SM8450_MSS>;
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MSS>;
power-domain-names = "cx", "mss";
memory-region = <&mpss_mem>;
@@ -2613,7 +2614,7 @@
reg = <0 0x0aaf0000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_VIDEO_AHB_CLK>;
- power-domains = <&rpmhpd SM8450_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -2705,7 +2706,7 @@
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
- power-domains = <&rpmhpd SM8450_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -2767,7 +2768,7 @@
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
- power-domains = <&rpmhpd SM8450_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
@@ -2859,7 +2860,7 @@
#sound-dai-cells = <0>;
operating-points-v2 = <&dp_opp_table>;
- power-domains = <&rpmhpd SM8450_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
status = "disabled";
@@ -2925,7 +2926,7 @@
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
operating-points-v2 = <&mdss_dsi_opp_table>;
- power-domains = <&rpmhpd SM8450_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&mdss_dsi0_phy>;
phy-names = "dsi";
@@ -3017,7 +3018,7 @@
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
operating-points-v2 = <&mdss_dsi_opp_table>;
- power-domains = <&rpmhpd SM8450_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&mdss_dsi1_phy>;
phy-names = "dsi";
@@ -3085,7 +3086,7 @@
<0>,
<0>, /* dp3 */
<0>;
- power-domains = <&rpmhpd SM8450_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -4243,7 +4244,7 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
iommus = <&apps_smmu 0x4a0 0x0>;
- power-domains = <&rpmhpd SM8450_CX>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
dma-coherent;
--
2.7.4
Powered by blists - more mailing lists