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Message-ID: <8194aa14-6465-5b4d-1b13-72c6af818f82@quicinc.com>
Date: Thu, 20 Jul 2023 15:25:20 +0530
From: Sricharan Ramabadhran <quic_srichara@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Greg KH <gregkh@...uxfoundation.org>, <agross@...nel.org>,
<andersson@...nel.org>, <konrad.dybcio@...aro.org>,
<robh@...nel.org>, <mani@...nel.org>, <lpieralisi@...nel.org>,
<bhelgaas@...gle.com>, <kw@...ux.com>,
<linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-pci@...r.kernel.org>, <stable@...r.kernel.org>
Subject: Re: [PATCH V4] PCI: qcom: Fixing broken pcie bring up for 2_3_3
configs ops
On 7/17/2023 11:23 PM, Dmitry Baryshkov wrote:
> On Mon, 17 Jul 2023 at 20:16, Sricharan Ramabadhran
> <quic_srichara@...cinc.com> wrote:
>>
>>
>>
>> On 7/17/2023 7:09 PM, Greg KH wrote:
>>> On Mon, Jul 17, 2023 at 12:25:35PM +0530, Sricharan Ramabadhran wrote:
>>>> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074
>>>> 2_3_3 post_init ops. PCIe slave addr size was initially set
>>>> to 0x358, but was wrongly changed to 0x168 as a part of
>>>> commit 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from
>>>> register definitions"). Fixing it, by using the right macro
>>>> PARF_SLV_ADDR_SPACE_SIZE and remove the unused
>>>> PARF_SLV_ADDR_SPACE_SIZE_2_3_3.
>>>
>>> Note, you do have a full 72 columns to use, no need to make it smaller.
>>
>> ok sure
>>
>>>
>>>> Without this pcie bring up on IPQ8074 is broken now.
>>>
>>> I do not understand, something that used to work now breaks, or this is
>>> preventing a new chip from being "brought up"?
>>>
>>
>> yes, ipq8074 pcie which was previously working is broken now.
>> This patch fixes it.
>
> So, you need to describe what is broken and why. Mere "it is broken,
> fix it" is not enough.
ok sure, will change the subject and explicitly state in commit log
how pcie enumeration is broken up.
Regards,
Sricharan
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