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Message-ID: <e9c80a369f3f64d0c84e4b7230daed4e7e0f8ff3.camel@intel.com>
Date: Thu, 20 Jul 2023 13:09:06 +0000
From: "Winiarska, Iwona" <iwona.winiarska@...el.com>
To: "linux@...ck-us.net" <linux@...ck-us.net>,
"linux-hwmon@...r.kernel.org" <linux-hwmon@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"Solanki, Naresh" <naresh.solanki@...ements.com>,
"jdelvare@...e.com" <jdelvare@...e.com>
CC: "Rudolph, Patrick" <patrick.rudolph@...ements.com>
Subject: Re: [PATCH v2 2/3] hwmon: (peci/cputemp) Add Intel Sapphire Rapids
support
On Wed, 2023-07-19 at 06:34 -0700, Guenter Roeck wrote:
> On 7/12/23 02:12, Naresh Solanki wrote:
> > From: Patrick Rudolph <patrick.rudolph@...ements.com>
> >
> > Add support to read DTS for reading Intel Sapphire Rapids platform.
> >
> > Signed-off-by: Patrick Rudolph <patrick.rudolph@...ements.com>
> > Signed-off-by: Naresh Solanki <Naresh.Solanki@...ements.com>
>
> I don't know what the plan is to apply this and the next patch, since
> (I assume) it depends on the first patch of the series. Assuming it will
> be applied through the peci tree:
>
> Acked-by: Guenter Roeck <linux@...ck-us.net>
Sure - it can go through the PECI tree once my review comments are addressed.
Thanks
-Iwona
>
> Guenter
>
> > ---
> > Changes in V2:
> > - Refactored from previous patchset as seperate patch based on subsystem.
> > ---
> > drivers/hwmon/peci/cputemp.c | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/drivers/hwmon/peci/cputemp.c b/drivers/hwmon/peci/cputemp.c
> > index e5b65a382772..a812c15948d9 100644
> > --- a/drivers/hwmon/peci/cputemp.c
> > +++ b/drivers/hwmon/peci/cputemp.c
> > @@ -363,6 +363,7 @@ static int init_core_mask(struct peci_cputemp *priv)
> > switch (peci_dev->info.model) {
> > case INTEL_FAM6_ICELAKE_X:
> > case INTEL_FAM6_ICELAKE_D:
> > + case INTEL_FAM6_SAPPHIRERAPIDS_X:
> > ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg-
> > >dev,
> > reg->func, reg->offset + 4,
> > &data);
> > if (ret)
> > @@ -531,6 +532,13 @@ static struct resolved_cores_reg resolved_cores_reg_icx
> > = {
> > .offset = 0xd0,
> > };
> >
> > +static struct resolved_cores_reg resolved_cores_reg_spr = {
> > + .bus = 31,
> > + .dev = 30,
> > + .func = 6,
> > + .offset = 0x80,
> > +};
> > +
> > static const struct cpu_info cpu_hsx = {
> > .reg = &resolved_cores_reg_hsx,
> > .min_peci_revision = 0x33,
> > @@ -549,6 +557,12 @@ static const struct cpu_info cpu_icx = {
> > .thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
> > };
> >
> > +static const struct cpu_info cpu_spr = {
> > + .reg = &resolved_cores_reg_spr,
> > + .min_peci_revision = 0x40,
> > + .thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
> > +};
> > +
> > static const struct auxiliary_device_id peci_cputemp_ids[] = {
> > {
> > .name = "peci_cpu.cputemp.hsx",
> > @@ -574,6 +588,10 @@ static const struct auxiliary_device_id
> > peci_cputemp_ids[] = {
> > .name = "peci_cpu.cputemp.icxd",
> > .driver_data = (kernel_ulong_t)&cpu_icx,
> > },
> > + {
> > + .name = "peci_cpu.cputemp.spr",
> > + .driver_data = (kernel_ulong_t)&cpu_spr,
> > + },
> > { }
> > };
> > MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids);
>
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