linux-kernel - [PATCH] drm/amd/pm: open brace '{' following struct go on the same line

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Message-ID: <9bb658b64109e1e60afdf82906ae3e03@208suo.com>
Date:   Fri, 21 Jul 2023 11:27:18 +0800
From:   sunran001@...suo.com
To:     alexander.deucher@....com, airlied@...il.com, daniel@...ll.ch
Cc:     amd-gfx@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH] drm/amd/pm: open brace '{' following struct go on the same
 line

ERROR: open brace '{' following struct go on the same line

Signed-off-by: Ran Sun <sunran001@...suo.com>
---
  .../gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h  | 21 +++++++------------
  1 file changed, 7 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
index 1dc7a065a6d4..251ed011b3b0 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
@@ -41,8 +41,7 @@
  #define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x83        // OverDrive 8 
Table Version 0.2
  #define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving 
Clock Table Version 1.00

-enum SMU_13_0_0_ODFEATURE_CAP
-{
+enum SMU_13_0_0_ODFEATURE_CAP {
      SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0,
      SMU_13_0_0_ODCAP_UCLK_LIMITS,
      SMU_13_0_0_ODCAP_POWER_LIMIT,
@@ -62,8 +61,7 @@ enum SMU_13_0_0_ODFEATURE_CAP
      SMU_13_0_0_ODCAP_COUNT,
  };

-enum SMU_13_0_0_ODFEATURE_ID
-{
+enum SMU_13_0_0_ODFEATURE_ID {
      SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS           = 1 << 
SMU_13_0_0_ODCAP_GFXCLK_LIMITS,           //GFXCLK Limit feature
      SMU_13_0_0_ODFEATURE_UCLK_LIMITS             = 1 << 
SMU_13_0_0_ODCAP_UCLK_LIMITS,             //UCLK Limit feature
      SMU_13_0_0_ODFEATURE_POWER_LIMIT             = 1 << 
SMU_13_0_0_ODCAP_POWER_LIMIT,             //Power Limit feature
@@ -85,8 +83,7 @@ enum SMU_13_0_0_ODFEATURE_ID

  #define SMU_13_0_0_MAX_ODFEATURE 32 //Maximum Number of OD Features

-enum SMU_13_0_0_ODSETTING_ID
-{
+enum SMU_13_0_0_ODSETTING_ID {
      SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0,
      SMU_13_0_0_ODSETTING_GFXCLKFMIN,
      SMU_13_0_0_ODSETTING_UCLKFMIN,
@@ -123,8 +120,7 @@ enum SMU_13_0_0_ODSETTING_ID
  };
  #define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings

-enum SMU_13_0_0_PWRMODE_SETTING
-{
+enum SMU_13_0_0_PWRMODE_SETTING {
      SMU_13_0_0_PMSETTING_POWER_LIMIT_QUIET = 0,
      SMU_13_0_0_PMSETTING_POWER_LIMIT_BALANCE,
      SMU_13_0_0_PMSETTING_POWER_LIMIT_TURBO,
@@ -144,8 +140,7 @@ enum SMU_13_0_0_PWRMODE_SETTING
  };
  #define SMU_13_0_0_MAX_PMSETTING 32 //Maximum Number of PowerMode 
Settings

-struct smu_13_0_0_overdrive_table
-{
+struct smu_13_0_0_overdrive_table {
      uint8_t revision;                             //Revision = 
SMU_13_0_0_PP_OVERDRIVE_VERSION
      uint8_t reserve[3];                           //Zero filled field 
reserved for future use
      uint32_t feature_count;                       //Total number of 
supported features
@@ -156,8 +151,7 @@ struct smu_13_0_0_overdrive_table
      int16_t pm_setting[SMU_13_0_0_MAX_PMSETTING]; //Optimized power 
mode feature settings
  };

-enum SMU_13_0_0_PPCLOCK_ID
-{
+enum SMU_13_0_0_PPCLOCK_ID {
      SMU_13_0_0_PPCLOCK_GFXCLK = 0,
      SMU_13_0_0_PPCLOCK_SOCCLK,
      SMU_13_0_0_PPCLOCK_UCLK,
@@ -175,8 +169,7 @@ enum SMU_13_0_0_PPCLOCK_ID
  };
  #define SMU_13_0_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks

-struct smu_13_0_0_powerplay_table
-{
+struct smu_13_0_0_powerplay_table {
      struct atom_common_table_header header; //For SMU13, 
header.format_revision = 15, header.content_revision = 0
      uint8_t table_revision;                 //For SMU13, table_revision 
= 2
      uint8_t padding;