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Message-Id: <20230719-imx8mp_enet_qos_use_125mhz_clock-v2-1-eed15d74bfd1@pengutronix.de>
Date: Fri, 21 Jul 2023 05:51:48 +0200
From: Johannes Zink <j.zink@...gutronix.de>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>
Cc: patchwork-jzi@...gutronix.de, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Johannes Zink <j.zink@...gutronix.de>
Subject: [PATCH v2] arm64: dts: imx8mp: use correct clock for eqos
timestamping counter
The i.MX8MP Reference Manual rev 1 06/2021, section 11.7.2.5 "Timestamp
Support" indicates the PTP timestamp clock expects a typical frequency
of 125MHz.
As this also improves the precision of the measured timestamps: assign
appropriate 125MHz Clock parent. As no one except the timestamping
counter uses this clock, there are no side-effects of this change in
other peripherals.
Signed-off-by: Johannes Zink <j.zink@...gutronix.de>
---
Changes in v2:
- not only set assigned-clock-parents but alkso assigned-clock-rates for
IMX8MP_CLK_ENET_QOS_TIMER to 125MHz (found by Fabio's review -
thanks!)
- Link to v1: https://lore.kernel.org/r/20230719-imx8mp_enet_qos_use_125mhz_clock-v1-1-782c9ac6e121@pengutronix.de
---
Changes:
v1 -> v2: Worked in Fabio's Feedback - Thank you for your review!
- not only set assigned clock parent to 125MHz but also
set the assigned clock rate of IMX8MP_CLK_ENET_QOS_TIMER
to 125MHz
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 6f2f50e1639c..84ecf07affb3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1334,9 +1334,9 @@ eqos: ethernet@...f0000 {
<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
<&clk IMX8MP_CLK_ENET_QOS>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
- <&clk IMX8MP_SYS_PLL2_100M>,
+ <&clk IMX8MP_SYS_PLL2_125M>,
<&clk IMX8MP_SYS_PLL2_125M>;
- assigned-clock-rates = <0>, <100000000>, <125000000>;
+ assigned-clock-rates = <0>, <125000000>, <125000000>;
nvmem-cells = <ð_mac2>;
nvmem-cell-names = "mac-address";
intf_mode = <&gpr 0x4>;
---
base-commit: ba345b77fae7054d0cbd033283c47033e45db6d8
change-id: 20230719-imx8mp_enet_qos_use_125mhz_clock-1c4611c979ba
Best regards,
--
Johannes Zink <j.zink@...gutronix.de>
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