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Message-ID: <20230721214740.256602-1-Smita.KoralahalliChannabasappa@amd.com>
Date: Fri, 21 Jul 2023 21:47:37 +0000
From: Smita Koralahalli <Smita.KoralahalliChannabasappa@....com>
To: <linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-cxl@...r.kernel.org>
CC: Bjorn Helgaas <bhelgaas@...gle.com>, <oohall@...il.com>,
Lukas Wunner <lukas@...ner.de>,
Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@...ux.intel.com>,
Mahesh J Salgaonkar <mahesh@...ux.ibm.com>,
Alison Schofield <alison.schofield@...el.com>,
"Vishal Verma" <vishal.l.verma@...el.com>,
Ira Weiny <ira.weiny@...el.com>,
"Ben Widawsky" <bwidawsk@...nel.org>,
Dan Williams <dan.j.williams@...el.com>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>,
Yazen Ghannam <yazen.ghannam@....com>,
Terry Bowman <terry.bowman@....com>,
Robert Richter <rrichter@....com>,
Smita Koralahalli <Smita.KoralahalliChannabasappa@....com>
Subject: [PATCH v2 0/3] PCI/AER, CXL: Fix appropriate _OSC check for CXL RAS Cap
This series of patches fixes the appropriate _OSC check for CXL RAS
registers.
First patch addresses the _OSC check.
Second patch moves around pcie_aer_is_native() function declaration to a
common location to be used by cxl/pci module and third patch reuses
pcie_aer_is_native() in cxl/pci module.
Link to v1:
https://lore.kernel.org/all/20230719192313.38591-1-Smita.KoralahalliChannabasappa@amd.com
Smita Koralahalli (3):
cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS
registers
PCI/AER: Export pcie_aer_is_native()
cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()
drivers/cxl/pci.c | 7 +++----
drivers/pci/pcie/aer.c | 1 +
drivers/pci/pcie/portdrv.h | 2 --
include/linux/aer.h | 2 ++
4 files changed, 6 insertions(+), 6 deletions(-)
--
2.17.1
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