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Message-ID: <20230721054619.2366510-4-quic_ipkumar@quicinc.com>
Date: Fri, 21 Jul 2023 11:16:17 +0530
From: Praveenkumar I <quic_ipkumar@...cinc.com>
To: <agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <amitk@...nel.org>,
<thara.gopinath@...il.com>, <rafael@...nel.org>,
<daniel.lezcano@...aro.org>, <rui.zhang@...el.com>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-pm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: <quic_varada@...cinc.com>
Subject: [PATCH v5 3/5] arm64: dts: qcom: ipq5332: Add tsens node
IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsense
node with nvmem cells for calibration data.
Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
---
[v5]:
No changes.
[v4]:
No changes.
[v3]:
Reordered device nodes according to the address.
[v2]:
Included qfprom nodes only for available sensors and removed
the offset suffix.
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 66 +++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 8bfc2db44624..026f99fda00c 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -150,6 +150,46 @@ qfprom: efuse@...00 {
reg = <0x000a4000 0x721>;
#address-cells = <1>;
#size-cells = <1>;
+
+ s11: s11@3a5 {
+ reg = <0x3a5 0x1>;
+ bits = <4 4>;
+ };
+
+ s12: s12@3a6 {
+ reg = <0x3a6 0x1>;
+ bits = <0 4>;
+ };
+
+ s13: s13@3a6 {
+ reg = <0x3a6 0x1>;
+ bits = <4 4>;
+ };
+
+ s14: s14@3ad {
+ reg = <0x3ad 0x2>;
+ bits = <7 4>;
+ };
+
+ s15: s15@3ae {
+ reg = <0x3ae 0x1>;
+ bits = <3 4>;
+ };
+
+ tsens_mode: mode@3e1 {
+ reg = <0x3e1 0x1>;
+ bits = <0 3>;
+ };
+
+ tsens_base0: base0@3e1 {
+ reg = <0x3e1 0x2>;
+ bits = <3 10>;
+ };
+
+ tsens_base1: base1@3e2 {
+ reg = <0x3e2 0x2>;
+ bits = <5 10>;
+ };
};
rng: rng@...00 {
@@ -159,6 +199,32 @@ rng: rng@...00 {
clock-names = "core";
};
+ tsens: thermal-sensor@...000 {
+ compatible = "qcom,ipq5332-tsens";
+ reg = <0x4a9000 0x1000>,
+ <0x4a8000 0x1000>;
+ nvmem-cells = <&tsens_mode>,
+ <&tsens_base0>,
+ <&tsens_base1>,
+ <&s11>,
+ <&s12>,
+ <&s13>,
+ <&s14>,
+ <&s15>;
+ nvmem-cell-names = "mode",
+ "base0",
+ "base1",
+ "s11",
+ "s12",
+ "s13",
+ "s14",
+ "s15";
+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "combined";
+ #qcom,sensors = <5>;
+ #thermal-sensor-cells = <1>;
+ };
+
tlmm: pinctrl@...0000 {
compatible = "qcom,ipq5332-tlmm";
reg = <0x01000000 0x300000>;
--
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