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Message-ID: <CAJF2gTTBbHDr4yD=aeof_h1WM6b_CD-yJcs6R5g=jt4-NdAR8w@mail.gmail.com>
Date:   Fri, 21 Jul 2023 20:06:53 -0400
From:   Guo Ren <guoren@...nel.org>
To:     Alexandre Ghiti <alex@...ti.fr>
Cc:     palmer@...osinc.com, paul.walmsley@...ive.com, falcon@...ylab.org,
        bjorn@...nel.org, conor.dooley@...rochip.com,
        linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH] riscv: Add HAVE_IOREMAP_PROT support

On Mon, Jul 17, 2023 at 5:07 AM Alexandre Ghiti <alex@...ti.fr> wrote:
>
> Hi Guo,
>
> On 16/07/2023 17:20, guoren@...nel.org wrote:
> > From: Guo Ren <guoren@...ux.alibaba.com>
> >
> > Add pte_pgprot macro, then riscv could have HAVE_IOREMAP_PROT,
> > which will enable generic_access_phys() code, it is useful for
> > debug, eg, gdb.
>
>
> I don't understand, we already have the generic ioremap_prot()
> implementation since we select GENERIC_IOREMAP: shouldn't
> HAVE_IOREMAP_PROT imply that we have our own implementation?
They are different! See arch/arm64/Kconfig, which selects all of them.

HAVE_IOREMAP_PROT would enable your drivers/char/mem.c
generic_access_phys of mmap_mem_ops.

It's a small function enabling.

>
> Thanks,
>
> Alex
>
>
> > Because generic_access_phys() would call ioremap_prot()->
> > pgprot_nx() to disable excutable attribute, add definition
> > of pgprot_nx() for riscv.
> >
> > Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@...nel.org>
> > ---
> >   .../features/vm/ioremap_prot/arch-support.txt     |  2 +-
> >   arch/riscv/Kconfig                                |  1 +
> >   arch/riscv/include/asm/pgtable.h                  | 15 +++++++++++++++
> >   3 files changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt
> > index a24149e59d73..ea8c8a361455 100644
> > --- a/Documentation/features/vm/ioremap_prot/arch-support.txt
> > +++ b/Documentation/features/vm/ioremap_prot/arch-support.txt
> > @@ -21,7 +21,7 @@
> >       |    openrisc: | TODO |
> >       |      parisc: | TODO |
> >       |     powerpc: |  ok  |
> > -    |       riscv: | TODO |
> > +    |       riscv: |  ok  |
> >       |        s390: |  ok  |
> >       |          sh: |  ok  |
> >       |       sparc: | TODO |
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 4c07b9189c86..15900fa20797 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -117,6 +117,7 @@ config RISCV
> >       select HAVE_FUNCTION_ERROR_INJECTION
> >       select HAVE_GCC_PLUGINS
> >       select HAVE_GENERIC_VDSO if MMU && 64BIT
> > +     select HAVE_IOREMAP_PROT
> >       select HAVE_IRQ_TIME_ACCOUNTING
> >       select HAVE_KPROBES if !XIP_KERNEL
> >       select HAVE_KPROBES_ON_FTRACE if !XIP_KERNEL
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index 75970ee2bda2..c9552a161f90 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -415,6 +415,11 @@ static inline pte_t pte_mkhuge(pte_t pte)
> >       return pte;
> >   }
> >
> > +static inline pgprot_t pte_pgprot(pte_t pte)
> > +{
> > +     return __pgprot(pte_val(pte) & ~_PAGE_PFN_MASK);
> > +}
> > +
> >   #ifdef CONFIG_NUMA_BALANCING
> >   /*
> >    * See the comment in include/asm-generic/pgtable.h
> > @@ -573,6 +578,16 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> >       return ptep_test_and_clear_young(vma, address, ptep);
> >   }
> >
> > +#define pgprot_nx pgprot_nx
> > +static inline pgprot_t pgprot_nx(pgprot_t _prot)
> > +{
> > +     unsigned long prot = pgprot_val(_prot);
> > +
> > +     prot &= ~_PAGE_EXEC;
> > +
> > +     return __pgprot(prot);
> > +}
> > +
> >   #define pgprot_noncached pgprot_noncached
> >   static inline pgprot_t pgprot_noncached(pgprot_t _prot)
> >   {



-- 
Best Regards
 Guo Ren

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