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Message-ID: <20230722-coleslaw-breeder-40827e23f717@spud>
Date: Sat, 22 Jul 2023 12:42:09 +0100
From: Conor Dooley <conor@...nel.org>
To: Sebastian Reichel <sebastian.reichel@...labora.com>
Cc: Heiko Stuebner <heiko@...ech.de>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
linux-rockchip@...ts.infradead.org, linux-usb@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, kernel@...labora.com
Subject: Re: [PATCH v2 1/3] dt-bindings: usb: add rk3588 compatible to
rockchip,dwc3
On Thu, Jul 20, 2023 at 07:36:41PM +0200, Sebastian Reichel wrote:
> RK3588 has three DWC3 controllers. Two of them are fully functional in
> host, device and OTG mode including USB2 support. They are connected to
> dedicated PHYs, that also support USB-C's DisplayPort alternate mode.
>
> The third controller is connected to one of the combphy's shared
> with PCIe and SATA. It can only be used in host mode and does not
> support USB2. Compared to the other controllers this one needs
> some extra clocks.
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@...labora.com>
I feel like I say it a bunch for some of these Rockchip bindings
patches, but if you're adding more clocks for some SoCs, should some
per-SoC constraints not also be added?
> ---
> .../devicetree/bindings/usb/rockchip,dwc3.yaml | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> index 291844c8f3e1..cbc3e55e05e1 100644
> --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> @@ -30,6 +30,7 @@ select:
> enum:
> - rockchip,rk3328-dwc3
> - rockchip,rk3568-dwc3
> + - rockchip,rk3588-dwc3
> required:
> - compatible
>
> @@ -39,6 +40,7 @@ properties:
> - enum:
> - rockchip,rk3328-dwc3
> - rockchip,rk3568-dwc3
> + - rockchip,rk3588-dwc3
> - const: snps,dwc3
>
> reg:
> @@ -58,7 +60,9 @@ properties:
> Master/Core clock, must to be >= 62.5 MHz for SS
> operation and >= 30MHz for HS operation
> - description:
> - Controller grf clock
> + Controller grf clock OR UTMI clock
> + - description:
> + PIPE clock
>
> clock-names:
> minItems: 3
> @@ -66,7 +70,10 @@ properties:
> - const: ref_clk
> - const: suspend_clk
> - const: bus_clk
> - - const: grf_clk
> + - enum:
> + - grf_clk
> + - utmi
> + - const: pipe
>
> power-domains:
> maxItems: 1
> --
> 2.40.1
>
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