linux-kernel - Re: [PATCH v5 4/6] soc: qcom: Add LLCC support for multi channel DDR

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <6971e2d5-e97d-cb60-473a-e1966e3818cb@quicinc.com>
Date:   Mon, 24 Jul 2023 18:10:38 +0530
From:   Mukesh Ojha <quic_mojha@...cinc.com>
To:     Komal Bajaj <quic_kbajaj@...cinc.com>, <agross@...nel.org>,
        <andersson@...nel.org>, <konrad.dybcio@...aro.org>,
        <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <conor+dt@...nel.org>, <srinivas.kandagatla@...aro.org>
CC:     <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 4/6] soc: qcom: Add LLCC support for multi channel DDR



On 7/24/2023 2:11 PM, Komal Bajaj wrote:
> Add LLCC support for multi channel DDR configuration
> based on a feature register.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@...cinc.com>
> ---
>   drivers/soc/qcom/llcc-qcom.c | 26 +++++++++++++++++++++++++-
>   1 file changed, 25 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 321f8d2079f7..1d2b08dfecea 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -12,6 +12,7 @@
>   #include <linux/kernel.h>
>   #include <linux/module.h>
>   #include <linux/mutex.h>
> +#include <linux/nvmem-consumer.h>
>   #include <linux/of.h>
>   #include <linux/of_device.h>
>   #include <linux/regmap.h>
> @@ -997,6 +998,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev,
>   	return ret;
>   }
>   
> +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index)
> +{
> +	int ret;
> +
> +	ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index);
> +	if (ret == -ENOENT || ret == -EOPNOTSUPP) {
> +		*cfg_index = 0;
> +		return 0;
> +	}
> +
> +	return ret;
> +}
> +
>   static int qcom_llcc_remove(struct platform_device *pdev)
>   {
>   	/* Set the global pointer to a error code to avoid referencing it */
> @@ -1033,6 +1047,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>   	const struct qcom_llcc_config *cfg;
>   	const struct llcc_slice_config *llcc_cfg;
>   	u32 sz;
> +	u8 cfg_index;
>   	u32 version;
>   	struct regmap *regmap;
>   
> @@ -1050,7 +1065,16 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>   	}
>   
>   	cfgs = of_device_get_match_data(&pdev->dev);
> -	cfg = &cfgs->llcc_config[0];
> +	ret = qcom_llcc_get_cfg_index(pdev, &cfg_index);
> +	 if (ret)

alignment.. ?

-Mukesh

> +		goto err;
> +
> +	if (cfg_index >= cfgs->num_cfgs) {
> +		ret = -EINVAL;
> +		goto err;
> +	}
> +
> +	cfg = &cfgs->llcc_config[cfg_index];
>   
>   	ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
>   	if (ret)