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Message-ID: <64da6d98-953f-f813-7184-e69b1c8bb28e@amd.com>
Date:   Mon, 24 Jul 2023 14:59:08 -0700
From:   Smita Koralahalli <Smita.KoralahalliChannabasappa@....com>
To:     Sathyanarayanan Kuppuswamy 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>,
        linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-cxl@...r.kernel.org
Cc:     Bjorn Helgaas <bhelgaas@...gle.com>, oohall@...il.com,
        Lukas Wunner <lukas@...ner.de>,
        Mahesh J Salgaonkar <mahesh@...ux.ibm.com>,
        Alison Schofield <alison.schofield@...el.com>,
        Vishal Verma <vishal.l.verma@...el.com>,
        Ira Weiny <ira.weiny@...el.com>,
        Ben Widawsky <bwidawsk@...nel.org>,
        Dan Williams <dan.j.williams@...el.com>,
        Jonathan Cameron <Jonathan.Cameron@...wei.com>,
        Yazen Ghannam <yazen.ghannam@....com>,
        Terry Bowman <terry.bowman@....com>,
        Robert Richter <rrichter@....com>
Subject: Re: [PATCH v2 1/3] cxl/pci: Fix appropriate checking for _OSC while
 handling CXL RAS registers


>> -	/* BIOS has CXL error control */
>> -	if (!host_bridge->native_cxl_error)
>> -		return -ENXIO;
>> +	/* BIOS has PCIe AER error control */
>> +	if (!host_bridge->native_aer)
>> +		return 0;
> 
> Why not directly use pcie_aer_is_native() here?
Yeah, this was in my v1. But changed as per Robert's comments, to be 
applicable for automated backports..

https://lore.kernel.org/all/ZLkxiZv3lWfazwVH@rric.localdomain/

Please advice.

Thanks,
Smita
> 
>>   
>>   	rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);
>>   	if (rc)
> 

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