linux-kernel - Re: [PATCH v1 3/3] perf arm-spe: Support data source for Cortex-X4 CPU

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Message-ID: <c784911e-72f4-8150-530b-234978546a45@arm.com>
Date:   Mon, 24 Jul 2023 12:27:31 +0530
From:   Anshuman Khandual <anshuman.khandual@....com>
To:     Leo Yan <leo.yan@...aro.org>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        John Garry <john.g.garry@...cle.com>,
        James Clark <james.clark@....com>,
        Mike Leach <mike.leach@...aro.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Ian Rogers <irogers@...gle.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        D Scott Phillips <scott@...amperecomputing.com>,
        Marc Zyngier <maz@...nel.org>,
        German Gomez <german.gomez@....com>,
        Ali Saidi <alisaidi@...zon.com>,
        Jing Zhang <renyu.zj@...ux.alibaba.com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-perf-users@...r.kernel.org, fissure2010@...il.com
Subject: Re: [PATCH v1 3/3] perf arm-spe: Support data source for Cortex-X4
 CPU



On 7/17/23 11:13, Leo Yan wrote:
> We have a CPU list to maintain Neoverse CPUs (N1/N2/V2), this list is
> used for parsing data source packet.  Since Cortex-x4 CPU shares the
> same data source format with Neoverse CPUs, this commit adds Cortex-x4
> CPU into the CPU list so we can reuse the parsing logic.
> 
> The CPU list was assumed for only Neoverse CPUs, but now Cortex-X4 has
> been added into the list.  To avoid Neoverse specific naming, this patch
> renames the variables and function as the default data source format.
> 
> Signed-off-by: Leo Yan <leo.yan@...aro.org>
> ---
>  tools/perf/util/arm-spe.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
> index afbd5869f6bf..c2cdb9f2e188 100644
> --- a/tools/perf/util/arm-spe.c
> +++ b/tools/perf/util/arm-spe.c
> @@ -409,15 +409,16 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq,
>  	return arm_spe_deliver_synth_event(spe, speq, event, &sample);
>  }
>  
> -static const struct midr_range neoverse_spe[] = {
> +static const struct midr_range cpus_use_default_data_src[] = {

Is not 'cpus_use_default_data_src' too long ? 'use' could be dropped ?

>  	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
>  	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
>  	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
> +	MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
>  	{},
>  };
>  
> -static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *record,
> -						union perf_mem_data_src *data_src)
> +static void arm_spe__synth_data_source_default(const struct arm_spe_record *record,
> +					       union perf_mem_data_src *data_src)
>  {
>  	/*
>  	 * Even though four levels of cache hierarchy are possible, no known
> @@ -518,7 +519,8 @@ static void arm_spe__synth_data_source_generic(const struct arm_spe_record *reco
>  static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr)
>  {
>  	union perf_mem_data_src	data_src = { .mem_op = PERF_MEM_OP_NA };
> -	bool is_neoverse = is_midr_in_range_list(midr, neoverse_spe);
> +	bool is_default_dc =

_dc stands for ?

> +		is_midr_in_range_list(midr, cpus_use_default_data_src);
>  
>  	if (record->op & ARM_SPE_OP_LD)
>  		data_src.mem_op = PERF_MEM_OP_LOAD;
> @@ -527,8 +529,8 @@ static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 m
>  	else
>  		return 0;
>  
> -	if (is_neoverse)
> -		arm_spe__synth_data_source_neoverse(record, &data_src);
> +	if (is_default_dc)
> +		arm_spe__synth_data_source_default(record, &data_src);
>  	else
>  		arm_spe__synth_data_source_generic(record, &data_src);
>