linux-kernel - Re: [RFC PATCH v2] Documentation/page_tables: Add info about MMU/TLB and Page Faults

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Message-ID: <20230724105505.000060c7@Huawei.com>
Date:   Mon, 24 Jul 2023 10:55:05 +0100
From:   Jonathan Cameron <Jonathan.Cameron@...wei.com>
To:     "Fabio M. De Francesco" <fmdefrancesco@...il.com>
CC:     Jonathan Corbet <corbet@....net>,
        Linus Walleij <linus.walleij@...aro.org>,
        Mike Rapoport <rppt@...nel.org>, <linux-doc@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-mm@...ck.org>,
        Andrew Morton <akpm@...ux-foundation.org>,
        "Bagas Sanjaya" <bagasdotme@...il.com>,
        Ira Weiny <ira.weiny@...el.com>,
        "Matthew Wilcox" <willy@...radead.org>,
        Randy Dunlap <rdunlap@...radead.org>
Subject: Re: [RFC PATCH v2] Documentation/page_tables: Add info about
 MMU/TLB and Page Faults

On Sun, 23 Jul 2023 14:07:09 +0200
"Fabio M. De Francesco" <fmdefrancesco@...il.com> wrote:

> Extend page_tables.rst by adding a section about the role of MMU and TLB
> in translating between virtual addresses and physical page frames.
> Furthermore explain the concept behind Page Faults and how the Linux
> kernel handles TLB misses. Finally briefly explain how and why to disable
> the page faults handler.
> 
> Cc: Andrew Morton <akpm@...ux-foundation.org>
> Cc: Bagas Sanjaya <bagasdotme@...il.com>
> Cc: Ira Weiny <ira.weiny@...el.com>
> Cc: Jonathan Cameron <Jonathan.Cameron@...wei.com>
> Cc: Jonathan Corbet <corbet@....net>
> Cc: Linus Walleij <linus.walleij@...aro.org>
> Cc: Matthew Wilcox <willy@...radead.org>
> Cc: Mike Rapoport <rppt@...nel.org>
> Cc: Randy Dunlap <rdunlap@...radead.org>
> Signed-off-by: Fabio M. De Francesco <fmdefrancesco@...il.com>

Hi Fabio,

Some superficial comments...

> ---
> 
> v1->v2: Add further information about lower level functions in the page
> fault handler and add information about how and why to disable / enable
> the page fault handler (provided a link to a Ira's patch that make use
> of pagefault_disable() to prevent deadlocks).
> 
> This is an RFC PATCH because of two reasons:
> 
> 1) I've heard that there is consensus about the need to revise and
> extend the MM documentation, but I'm not sure about whether or not
> developers need these kind of introductory information.
> 
> 2) While preparing this little patch I decided to take a quicj look at

Spell check your intro text.

> the code and found out it currently is not how I thought I remembered
> it. I'm especially speaking about the x86 case. I'm not sure that I've
> been able to properly understand what I described as a difference in
> workflow compared to most of the other architecture.
> 
> Therefore, for the two reasons explained above, I'd like to hear from
> people actively involved in MM. If this is not what you want, feel free
> to throw it away. Otherwise I'd be happy to write more on this and other
> MM topics. I'm looking forward for comments on this small work.
> 
>  Documentation/mm/page_tables.rst | 87 ++++++++++++++++++++++++++++++++
>  1 file changed, 87 insertions(+)
> 
> diff --git a/Documentation/mm/page_tables.rst b/Documentation/mm/page_tables.rst
> index 7840c1891751..2be56f50c88f 100644
> --- a/Documentation/mm/page_tables.rst
> +++ b/Documentation/mm/page_tables.rst
> @@ -152,3 +152,90 @@ Page table handling code that wishes to be architecture-neutral, such as the
>  virtual memory manager, will need to be written so that it traverses all of the
>  currently five levels. This style should also be preferred for
>  architecture-specific code, so as to be robust to future changes.
> +
> +
> +MMU, TLB, and Page Faults
> +=========================
> +
> +The Memory Management Unit (MMU) is a hardware component that handles virtual to
> +physical address translations. It uses a relatively small cache in hardware

It may use a relatively...
(I doubt Linux supports anything that doesn't have a TLB but they aren't required
 by some architectures - just a performance optmization that you 'can' add to
 an implementation.)

> +called the Translation Lookaside Buffer (TLB) to speed up these translations.
> +When a process wants to access a memory location, the CPU provides a virtual
> +address to the MMU, which then uses the TLB to quickly find the corresponding
> +physical address.
> +
> +However, sometimes the MMU can't find a valid translation in the TLB. This
> +could be because the process is trying to access a range of memory that it's not
> +allowed to, or because the memory hasn't been loaded into RAM yet.

It might not find it because this is first attempt to do the translation and
the MMU hasn't filled the TLB entry yet, or a capacity eviction has happened.
Basically failure to find it in the TLB doesn't mean we get a page fault
(unless you are on an ancient architecture where TLB entries are software filled
 which is definitely not the case for most modern ones).

>  When this
> +happens, the MMU triggers a page fault, which is a type of interrupt that

Hmm. Whilst similar to an interrupt I'd argue that it's not one..

> +signals the CPU to pause the current process and run a special function to
> +handle the fault.

...

Jonathan