linux-kernel - Re: [PATCH] riscv: Fix local irq restore when flags indicates irq disabled

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Message-ID: <CAEuiHnxkc3uO0==bo1R19SiS7DmuOQ5DMc2wjLbPxFhY4urYOA@mail.gmail.com>
Date:   Tue, 25 Jul 2023 14:25:03 +0800
From:   Xu Lu <luxujoy@...il.com>
To:     Conor Dooley <conor.dooley@...rochip.com>
Cc:     Ben Dooks <ben.dooks@...ethink.co.uk>, paul.walmsley@...ive.com,
        palmer@...belt.com, aou@...s.berkeley.edu,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        luxu.kernel@...edance.com
Subject: Re: [PATCH] riscv: Fix local irq restore when flags indicates irq disabled

On Mon, Jul 24, 2023 at 10:03 PM Conor Dooley
<conor.dooley@...rochip.com> wrote:
>
> On Mon, Jul 24, 2023 at 02:42:50PM +0100, Ben Dooks wrote:
> > On 24/07/2023 14:27, luxu.kernel wrote:
> > > When arch_local_irq_restore() is called with flags indicating irqs
> > > disabled, we need to clear SR_IE bit in CSR_STATUS, whereas current
> > > implementation based on csr_set() function only sets SR_IE bit of
> > > CSR_STATUS when SR_IE bit of flags is high and does nothing when
> > > SR_IE bit of flags is low.
> > >
> > > This commit supplies csr clear operation when calling irq restore
> > > function with flags indicating irq disabled.
> > >
> > > Signed-off-by: luxu.kernel <luxu.kernel@...edance.com>
> >
> > real-names are required for signoff
>
> And the From: address needs to match the signof, here the From: address
> is a gmail one.
>
> > > ---
> > >   arch/riscv/include/asm/irqflags.h | 5 ++++-
> > >   1 file changed, 4 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h
> > > index 08d4d6a5b7e9..7c31fc3c3559 100644
> > > --- a/arch/riscv/include/asm/irqflags.h
> > > +++ b/arch/riscv/include/asm/irqflags.h
> > > @@ -49,7 +49,10 @@ static inline int arch_irqs_disabled(void)
> > >   /* set interrupt enabled status */
> > >   static inline void arch_local_irq_restore(unsigned long flags)
> > >   {
> > > -   csr_set(CSR_STATUS, flags & SR_IE);
> > > +   if (flags & SR_IE)
> > > +           csr_set(CSR_STATUS, SR_IE);
> > > +   else
> > > +           csr_clear(CSR_STATUS, SR_IE);
> > >   }
> > >   #endif /* _ASM_RISCV_IRQFLAGS_H */
> >
> > I think this is correct, I wonder how long this has been going on
> > without anyone noticing?
>
> Code has been like this since 6d60b6ee0c97 ("RISC-V: Device, timer,
> IRQs, and the SBI"), committed on Tue Sep 26 15:26:47 2017 -0700.

Thanks for your reply. I will resend the patch with real name and
correct mailbox.