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Message-Id: <1690285689-30233-2-git-send-email-quic_vnivarth@quicinc.com>
Date: Tue, 25 Jul 2023 17:18:06 +0530
From: Vijaya Krishna Nivarthi <quic_vnivarth@...cinc.com>
To: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
broonie@...nel.org, linux-arm-msm@...r.kernel.org,
linux-spi@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: quic_msavaliy@...cinc.com, dianders@...omium.org, mka@...omium.org,
swboyd@...omium.org, quic_vtanuku@...cinc.com,
dan.carpenter@...aro.org,
Vijaya Krishna Nivarthi <quic_vnivarth@...cinc.com>
Subject: [PATCH 1/4] spi: spi-qcom-qspi: Ignore disabled interrupts' status in isr
During FIFO/DMA modes dynamic switching, only corresponding interrupts are
enabled. However its possible that FIFO related interrupt status registers
get set during DMA mode. For example WR_FIFO_EMPTY bit is set during DMA
TX.
Ignore such status bits so that they don't trip unwanted operations.
Suggested-by: Douglas Anderson <dianders@...omium.org>
Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@...cinc.com>
---
drivers/spi/spi-qcom-qspi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c
index a0ad980..b995542 100644
--- a/drivers/spi/spi-qcom-qspi.c
+++ b/drivers/spi/spi-qcom-qspi.c
@@ -603,6 +603,9 @@ static irqreturn_t qcom_qspi_irq(int irq, void *dev_id)
int_status = readl(ctrl->base + MSTR_INT_STATUS);
writel(int_status, ctrl->base + MSTR_INT_STATUS);
+ /* Ignore disabled interrupts */
+ int_status &= readl(ctrl->base + MSTR_INT_EN);
+
/* PIO mode handling */
if (ctrl->xfer.dir == QSPI_WRITE) {
if (int_status & WR_FIFO_EMPTY)
--
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