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Message-ID: <20230725125140.GC21640@pendragon.ideasonboard.com>
Date:   Tue, 25 Jul 2023 15:51:40 +0300
From:   Laurent Pinchart <laurent.pinchart@...asonboard.com>
To:     Marco Felsch <m.felsch@...gutronix.de>
Cc:     robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        conor+dt@...nel.org, shawnguo@...nel.org, kernel@...gutronix.de,
        festevam@...il.com, linux-imx@....com, dan.scally@...asonboard.com,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 1/4] arm64: dts: imx8mp-debix: remove unused fec
 pinctrl node

Hi Marco,

Thank you for the patch.

On Mon, Jul 17, 2023 at 06:51:24PM +0200, Marco Felsch wrote:
> The SoM A make use of the EQOS ethernet interface and not the FEC, so
> drop the FEC pinctrl node from the devicetree.
> 
> Fixes: c86d350aae68 ("arm64: dts: Add device tree for the Debix Model A Board")
> Signed-off-by: Marco Felsch <m.felsch@...gutronix.de>

I think the I/O board uses the FEC for its ethernet interface. It would
be nice to eventually move this to an I/O board overlay, but for now,

Reviewed-by: Laurent Pinchart <laurent.pinchart@...asonboard.com>

> ---
> Changelog:
> 
> v2:
> - new patch
> 
>  .../dts/freescale/imx8mp-debix-model-a.dts    | 22 -------------------
>  1 file changed, 22 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> index b4409349eb3f6..1004ab0abb131 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> @@ -355,28 +355,6 @@ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18				0x19
>  		>;
>  	};
>  
> -	pinctrl_fec: fecgrp {
> -		fsl,pins = <
> -			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC				0x3
> -			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO				0x3
> -			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0				0x91
> -			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1				0x91
> -			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2				0x91
> -			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3				0x91
> -			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC				0x91
> -			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL			0x91
> -			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0				0x1f
> -			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1				0x1f
> -			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2				0x1f
> -			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3				0x1f
> -			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL			0x1f
> -			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC				0x1f
> -			MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT			0x1f
> -			MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN			0x1f
> -			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19				0x19
> -		>;
> -	};
> -
>  	pinctrl_gpio_led: gpioledgrp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16				0x19

-- 
Regards,

Laurent Pinchart

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