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Message-Id: <20230726-sixth-uphill-66fbc1b5e5ce@spud>
Date:   Wed, 26 Jul 2023 17:15:20 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Emil Renner Berthing <emil.renner.berthing@...onical.com>,
        Conor Dooley <conor@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Minda Chen <minda.chen@...rfivetech.com>,
        devicetree@...r.kernel.org, linux-spi@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        William Qiu <william.qiu@...rfivetech.com>
Cc:     Conor Dooley <conor.dooley@...rochip.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Mark Brown <broonie@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Emil Renner Berthing <kernel@...il.dk>,
        Linus Walleij <linus.walleij@...aro.org>
Subject: Re: (subset) [PATCH v3 0/2] Add SPI module for StarFive JH7110 SoC

From: Conor Dooley <conor.dooley@...rochip.com>

On Mon, 24 Jul 2023 18:10:52 +0800, William Qiu wrote:
> This patchset adds initial rudimentary support for the StarFive
> SPI controller. And this driver will be used in StarFive's
> VisionFive 2 board. The first patch constrain minItems of clocks
> for JH7110 SPI and Patch 2 adds support for StarFive JH7110 SPI.
> 
> Changes v2->v3:
> - Rebaed to v6.5rc3.
> - Registered one more clock.
> - Dropped commit that changed the number of clocks in YAML.
> - Rewrited the commit comment.
> 
> [...]

Applied to riscv-dt-for-next, thanks!

[2/2] riscv: dts: starfive: Add spi node and pins configuration
      https://git.kernel.org/conor/c/74fb20c8f05d

Thanks,
Conor.

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