linux-kernel - Re: [PATCH v4 3/3] hwmon: (peci/dimmtemp) Add Sapphire Rapids support

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Message-ID: <b7e7b713045117db782341d74f69094e167b95c1.camel@intel.com>
Date:   Wed, 26 Jul 2023 20:22:29 +0000
From:   "Winiarska, Iwona" <iwona.winiarska@...el.com>
To:     "linux@...ck-us.net" <linux@...ck-us.net>,
        "linux-hwmon@...r.kernel.org" <linux-hwmon@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Solanki, Naresh" <naresh.solanki@...ements.com>,
        "jdelvare@...e.com" <jdelvare@...e.com>
CC:     "Rudolph, Patrick" <patrick.rudolph@...ements.com>
Subject: Re: [PATCH v4 3/3] hwmon: (peci/dimmtemp) Add Sapphire Rapids support

On Tue, 2023-07-25 at 12:43 +0200, Naresh Solanki wrote:
> From: Patrick Rudolph <patrick.rudolph@...ements.com>
> 
> Extend the functionality of hwmon (peci/dimmtemp) for Sapphire Rapids
> platform.
> 
> Add the corresponding Sapphire Rapids ID and threshold code.
> 
> The patch has been tested on a 4S system with 64 DIMMs installed.
> Verified read of DIMM temperature thresholds & temperature.
> 
> Signed-off-by: Patrick Rudolph <patrick.rudolph@...ements.com>
> Signed-off-by: Naresh Solanki <Naresh.Solanki@...ements.com>
> Acked-by: Guenter Roeck <linux@...ck-us.net>

Reviewed-by: Iwona Winiarska <iwona.winiarska@...el.com>

I'll apply it to peci-next.

Thanks
-Iwona

> ---
> Changes in V4:
> - Instead of using hard coded dimm temperature threshold, read from mmio
>   offset.
> - Change CHAN_RANK_MAX_ON_SPR to 8
> - Restore #define CHAN_RANK_MAX to previous assignment.
> - Update commit message.
> Changes in V3:
> - Update Acked-by in commit message.
> Changes in V2:
> - Update subject.
> ---
>  drivers/hwmon/peci/dimmtemp.c | 50 +++++++++++++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c
> index ce89da3937a0..5ca4d04e4b14 100644
> --- a/drivers/hwmon/peci/dimmtemp.c
> +++ b/drivers/hwmon/peci/dimmtemp.c
> @@ -30,6 +30,8 @@
>  #define DIMM_IDX_MAX_ON_ICX    2
>  #define CHAN_RANK_MAX_ON_ICXD  4
>  #define DIMM_IDX_MAX_ON_ICXD   2
> +#define CHAN_RANK_MAX_ON_SPR   8
> +#define DIMM_IDX_MAX_ON_SPR    2
>  
>  #define CHAN_RANK_MAX          CHAN_RANK_MAX_ON_HSX
>  #define DIMM_IDX_MAX           DIMM_IDX_MAX_ON_HSX
> @@ -534,6 +536,43 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int
> dimm_order, int chan_rank, u
>         return 0;
>  }
>  
> +static int
> +read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int
> chan_rank, u32 *data)
> +{
> +       u32 reg_val;
> +       u64 offset;
> +       int ret;
> +       u8 dev;
> +
> +       ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd4,
> &reg_val);
> +       if (ret || !(reg_val & BIT(31)))
> +               return -ENODATA; /* Use default or previous value */
> +
> +       ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd0,
> &reg_val);
> +       if (ret)
> +               return -ENODATA; /* Use default or previous value */
> +
> +       /*
> +        * Device 26, Offset 219a8: IMC 0 channel 0 -> rank 0
> +        * Device 26, Offset 299a8: IMC 0 channel 1 -> rank 1
> +        * Device 27, Offset 219a8: IMC 1 channel 0 -> rank 2
> +        * Device 27, Offset 299a8: IMC 1 channel 1 -> rank 3
> +        * Device 28, Offset 219a8: IMC 2 channel 0 -> rank 4
> +        * Device 28, Offset 299a8: IMC 2 channel 1 -> rank 5
> +        * Device 29, Offset 219a8: IMC 3 channel 0 -> rank 6
> +        * Device 29, Offset 299a8: IMC 3 channel 1 -> rank 7
> +        */
> +       dev = 26 + chan_rank / 2;
> +       offset = 0x219a8 + dimm_order * 4 + (chan_rank % 2) * 0x8000;
> +
> +       ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val),
> GET_CPU_BUS(reg_val),
> +                            dev, 0, offset, data);
> +       if (ret)
> +               return ret;
> +
> +       return 0;
> +}
> +
>  static const struct dimm_info dimm_hsx = {
>         .chan_rank_max  = CHAN_RANK_MAX_ON_HSX,
>         .dimm_idx_max   = DIMM_IDX_MAX_ON_HSX,
> @@ -576,6 +615,13 @@ static const struct dimm_info dimm_icxd = {
>         .read_thresholds = &read_thresholds_icx,
>  };
>  
> +static const struct dimm_info dimm_spr = {
> +       .chan_rank_max  = CHAN_RANK_MAX_ON_SPR,
> +       .dimm_idx_max   = DIMM_IDX_MAX_ON_SPR,
> +       .min_peci_revision = 0x40,
> +       .read_thresholds = &read_thresholds_spr,
> +};
> +
>  static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
>         {
>                 .name = "peci_cpu.dimmtemp.hsx",
> @@ -601,6 +647,10 @@ static const struct auxiliary_device_id
> peci_dimmtemp_ids[] = {
>                 .name = "peci_cpu.dimmtemp.icxd",
>                 .driver_data = (kernel_ulong_t)&dimm_icxd,
>         },
> +       {
> +               .name = "peci_cpu.dimmtemp.spr",
> +               .driver_data = (kernel_ulong_t)&dimm_spr,
> +       },
>         { }
>  };
>  MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);