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Message-ID: <20230726100609.72550-2-minda.chen@starfivetech.com>
Date: Wed, 26 Jul 2023 03:06:08 -0700
From: Minda Chen <minda.chen@...rfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@...onical.com>,
Conor Dooley <conor@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Subject: [dt-for-next v1 1/2] riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110
Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC.
Signed-off-by: Minda Chen <minda.chen@...rfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 90aabeac7b51..dbc1243a0e75 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -446,6 +446,27 @@ i2c2: i2c@...50000 {
status = "disabled";
};
+ usbphy0: phy@...00000 {
+ compatible = "starfive,jh7110-usb-phy";
+ reg = <0x0 0x10200000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+ <&stgcrg JH7110_STGCLK_USB0_APP_125>;
+ clock-names = "125m", "app_125m";
+ #phy-cells = <0>;
+ };
+
+ pciephy0: phy@...10000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x0 0x10210000 0x0 0x10000>;
+ #phy-cells = <0>;
+ };
+
+ pciephy1: phy@...20000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x0 0x10220000 0x0 0x10000>;
+ #phy-cells = <0>;
+ };
+
stgcrg: clock-controller@...30000 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x10230000 0x0 0x10000>;
--
2.25.1
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