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Message-Id: <20230727215141.53910-13-avolmat@me.com>
Date: Thu, 27 Jul 2023 21:51:36 +0000
From: Alain Volmat <avolmat@...com>
To: Patrice Chotard <patrice.chotard@...s.st.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: Alain Volmat <avolmat@...com>,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 12/14] ARM: dts: sti: addition of display nodes for stih418 platform
Addition of a first set of nodes (compositor/tvout/hdmi/dvo) in order
to allow graphic plane usage via HDMI or DVO on the stih418 based boards.
Signed-off-by: Alain Volmat <avolmat@...com>
---
arch/arm/boot/dts/st/stih418-clock.dtsi | 2 +-
arch/arm/boot/dts/st/stih418.dtsi | 154 ++++++++++++++++++++++++
2 files changed, 155 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/st/stih418-clock.dtsi b/arch/arm/boot/dts/st/stih418-clock.dtsi
index e1749e92a2e7..93641df58bf2 100644
--- a/arch/arm/boot/dts/st/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/st/stih418-clock.dtsi
@@ -17,7 +17,7 @@ clk_sysin: clk-sysin {
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <0>;
+ clock-frequency = <594000000>;
};
clocks {
diff --git a/arch/arm/boot/dts/st/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi
index b35b9b7a7ccc..b41de235fffa 100644
--- a/arch/arm/boot/dts/st/stih418.dtsi
+++ b/arch/arm/boot/dts/st/stih418.dtsi
@@ -6,6 +6,7 @@
#include "stih418-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
cpus {
#address-cells = <1>;
@@ -114,5 +115,158 @@ thermal@...0000 {
clocks = <&clk_sysin>;
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
};
+
+ sti-display-subsystem@0 {
+ compatible = "st,sti-display-subsystem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ reg = <0 0>;
+ assigned-clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_d2_flexgen CLK_TMDS_HDMI_DIV2>,
+ <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
+ <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
+ <&clk_s_c0_flexgen CLK_MAIN_DISP>,
+ <&clk_s_c0_flexgen CLK_AUX_DISP>,
+ <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+ <&clk_s_c0_flexgen CLK_PROC_MIXER>;
+
+ assigned-clock-parents = <0>,
+ <0>,
+ <&clk_tmdsout_hdmi>,
+ <&clk_tmdsout_hdmi>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_pll0 0>,
+ <&clk_s_c0_pll0 0>;
+
+ assigned-clock-rates = <297000000>,
+ <108000000>,
+ <297000000>,
+ <0>,
+ <74250000>,
+ <13500000>,
+ <400000000>,
+ <400000000>,
+ <355000000>,
+ <355000000>;
+
+ ranges;
+
+ sti_compo: sti-compositor@...0000 {
+ compatible = "st,stih418-compositor";
+ reg = <0xa600000 0x200000>;
+
+ clock-names = "compo_main",
+ "compo_aux",
+ "pix_main",
+ "pix_aux",
+ "proc_mixer";
+
+ clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+ <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+ <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
+ <&clk_s_c0_flexgen CLK_PROC_MIXER>;
+
+ reset-names = "compo-main", "compo-aux";
+ resets = <&softreset STIH407_COMPO_SOFTRESET>,
+ <&softreset STIH407_COMPO_SOFTRESET>;
+ st,vtg = <&vtg_main>, <&vtg_aux>;
+
+ status = "disabled";
+ };
+
+ sti_tvout: sti-tvout@...0000 {
+ compatible = "st,stih418-tvout";
+ reg = <0xa900000 0x1000>;
+ reg-names = "tvout-reg";
+ reset-names = "tvout";
+ resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
+ <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
+ <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
+ <&clk_s_d0_flexgen CLK_PCM_0>,
+ <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
+ <&clk_s_d2_flexgen CLK_HDDAC>;
+
+ assigned-clock-parents = <&clk_s_d2_quadfs 0>,
+ <&clk_tmdsout_hdmi>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d0_quadfs 0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 0>;
+ assigned-clock-rates = <74250000>,
+ <0>,
+ <74250000>,
+ <0>,
+ <74250000>,
+ <148500000>;
+
+ status = "disabled";
+ };
+
+ sti_dvo: sti-dvo@...0400 {
+ compatible = "st,stih407-dvo";
+ reg = <0xa800400 0x200>;
+ reg-names = "dvo-reg";
+ clock-names = "dvo_pix", "dvo",
+ "main_parent", "aux_parent";
+ clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>,
+ <&clk_s_d2_flexgen CLK_DVO>,
+ <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>;
+ status = "disabled";
+ };
+
+ sti_hdmi: sti-hdmi@...4000 {
+ compatible = "st,stih418-hdmi";
+ reg = <0xa804000 0x1000>;
+ reg-names = "hdmi-reg";
+ #sound-dai-cells = <0>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq";
+ clock-names = "pix",
+ "tmds",
+ "phy",
+ "audio",
+ "main_parent",
+ "aux_parent";
+
+ clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
+ <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
+ <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
+ <&clk_s_d0_flexgen CLK_PCM_0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>;
+
+ hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
+ reset-names = "hdmi";
+ resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
+
+ status = "disabled";
+ };
+ };
+
+ vtg_main: sti-vtg-main@...2800 {
+ compatible = "st,stih418-vtg";
+ reg = <0xa802800 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ vtg_aux: sti-vtg-aux@...0200 {
+ compatible = "st,stih418-vtg";
+ reg = <0xa800200 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
};
};
--
2.34.1
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