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Message-ID: <d6d4ab42-49b3-5704-0c2b-e3b2a607d835@intel.com>
Date: Thu, 27 Jul 2023 15:13:02 +0800
From: "Yang, Weijiang" <weijiang.yang@...el.com>
To: Chao Gao <chao.gao@...el.com>
CC: <seanjc@...gle.com>, <pbonzini@...hat.com>, <peterz@...radead.org>,
<john.allen@....com>, <kvm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <rick.p.edgecombe@...el.com>,
<binbin.wu@...ux.intel.com>,
Zhang Yi Z <yi.z.zhang@...ux.intel.com>
Subject: Re: [PATCH v4 12/20] KVM:VMX: Introduce CET VMCS fields and control
bits
On 7/27/2023 1:26 PM, Chao Gao wrote:
> On Thu, Jul 20, 2023 at 11:03:44PM -0400, Yang Weijiang wrote:
>> Two XSAVES state bits are introduced for CET:
>> IA32_XSS:[bit 11]: Control saving/restoring user mode CET states
>> IA32_XSS:[bit 12]: Control saving/restoring supervisor mode CET states.
>>
>> Six VMCS fields are introduced for CET:
>> {HOST,GUEST}_S_CET: Stores CET settings for kernel mode.
>> {HOST,GUEST}_SSP: Stores shadow stack pointer of current active task/thread.
>> {HOST,GUEST}_INTR_SSP_TABLE: Stores current active MSR_IA32_INT_SSP_TAB.
>>
>> On Intel platforms, two additional bits are defined in VM_EXIT and VM_ENTRY
>> control fields:
>> If VM_EXIT_LOAD_HOST_CET_STATE = 1, the host CET states are restored from
> Nit: s/VM_EXIT_LOAD_HOST_CET_STATE/VM_EXIT_LOAD_CET_STATE
>
> to align with the name you are actually using.
>
>> the following VMCS fields at VM-Exit:
>> HOST_S_CET
>> HOST_SSP
>> HOST_INTR_SSP_TABLE
>>
>> If VM_ENTRY_LOAD_GUEST_CET_STATE = 1, the guest CET states are loaded from
> Nit: s/VM_ENTRY_LOAD_GUEST_CET_STATE/VM_ENTRY_LOAD_CET_STATE
Sure, will change it, thanks a lot!
>
>> the following VMCS fields at VM-Entry:
>> GUEST_S_CET
>> GUEST_SSP
>> GUEST_INTR_SSP_TABLE
>>
>> Co-developed-by: Zhang Yi Z <yi.z.zhang@...ux.intel.com>
>> Signed-off-by: Zhang Yi Z <yi.z.zhang@...ux.intel.com>
>> Signed-off-by: Yang Weijiang <weijiang.yang@...el.com>
> Reviewed-by: Chao Gao <chao.gao@...el.com>
>
>> [...]
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