linux-kernel - Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <c5e44ec519f4d56a71d416cf43a375cdbf0b9358.camel@linuxfromscratch.org>
Date:   Thu, 27 Jul 2023 17:18:51 +0800
From:   Xi Ruoyao <xry111@...uxfromscratch.org>
To:     Jisheng Zhang <jszhang@...nel.org>
Cc:     Conor Dooley <conor.dooley@...rochip.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support

On Thu, 2023-07-27 at 08:54 +0800, Xi Ruoyao wrote:
> On Thu, 2023-07-27 at 08:14 +0800, Xi Ruoyao wrote:
> > On Wed, 2023-07-26 at 23:00 +0800, Jisheng Zhang wrote:
> > > which dts r u using? see below.
> > > 
> > > > 
> > > > Or maybe my toolchain (GCC 13.1.0, Binutils-2.40, with no patches) can
> > > > miscompile the kernel?
> > 
> > /* snip */
> > 
> > > > Boot HART ID              : 0
> > > > Boot HART Domain          : root
> > > > Boot HART Priv Version    : v1.11
> > > > Boot HART Base ISA        : rv64imafdcvx
> > > 
> > > what? I don't think the mainline dts provide v and x. 
> > 
> > I copied the compiled arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dtb
> > into /boot and loaded it with u-boot "load" command onto 0x46000000, and
> > passed this address to the booti command.
> > 
> > But maybe I've copied the wrong file or made some other mistake... I'll
> > recheck.
> 
> Hmm, and if I read OpenSBI code correctly, this line reflects the
> content of the misa CSR, not the DT riscv,isa value.
> 
> The log of successful boot provided by Drew also contains
> "rv64imafdcvx":
> 
> https://gist.github.com/pdp7/23259595a7570f1f11086d286e16dfb6

I tried a __show_reg call before the panic:

[    0.012953] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.5.0-rc3 #7
[    0.012967] Hardware name: Sipeed Lichee Pi 4A (DT)
[    0.012976] epc : ffffffff80c84a60 ra : 0000000000000000 sp : ffffffff8004dfee
[    0.012988]  gp : 0000000200000120 tp : ffffffff80c03d20 t0 : ffffffff80002d6c
[    0.012997]  t1 : ffffffff8004dfee t2 : ffffffff8004dfe6 s0 : ffffffff80c03d20
[    0.013005]  s1 : ffffffff80c966f0 a0 : ffffffff80c98140 a1 : 2000000000000000
[    0.013012]  a2 : 0000000000000043 a3 : 203a656c6f736e6f a4 : ffffffff80c03def
[    0.013021]  a5 : ffffffff80dcb4a0 a6 : 0000000000000001 a7 : 0000000000000014
[    0.013030]  s2 : 000000000000000a s3 : 0000000000000000 s4 : 0000000000000000
[    0.013036]  s5 : ffffffd9fef69740 s6 : 0000000000000008 s7 : 0000000000000032
[    0.013046]  s8 : 0000000000000002 s9 : ffffffff80c03df0 s10: ffffffff80dcb4e8
[    0.013056]  s11: ffffffff80dc7c80 t3 : ffffffff80c03d48 t4 : ffffffff80dcb2f0
[    0.013064]  t5 : ffffffff80c84a60 t6 : ffffffff80c10b98
[    0.013071] status: 0000000000000000 badaddr: 0000000000000001 cause: ffffffff80dcb4f7
[    0.013082] Kernel panic - not syncing: unexpected interrupt cause

I compared these with System.map and the result seems completely erratic
(for example, sp is out of init_stack, and gp is not __global_pointer$).