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Message-Id: <1690525040-77423-4-git-send-email-renyu.zj@linux.alibaba.com>
Date: Fri, 28 Jul 2023 14:17:18 +0800
From: Jing Zhang <renyu.zj@...ux.alibaba.com>
To: John Garry <john.g.garry@...cle.com>,
Ian Rogers <irogers@...gle.com>
Cc: Will Deacon <will@...nel.org>, Mark Rutland <mark.rutland@....com>,
Robin Murphy <robin.murphy@....com>,
Ilkka Koskinen <ilkka@...amperecomputing.com>,
Namhyung Kim <namhyung@...nel.org>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-perf-users@...r.kernel.org, linux-doc@...r.kernel.org,
Zhuo Song <zhuo.song@...ux.alibaba.com>,
Jing Zhang <renyu.zj@...ux.alibaba.com>,
Shuai Xue <xueshuai@...ux.alibaba.com>
Subject: [PATCH v5 3/5] perf test: Add pmu-event test for "Compat" and new event_field.
Add new event test for uncore system event which is used to verify the
functionality of "Compat" matching multiple identifiers and the new event
fields "EventIdCode" and "Type".
Signed-off-by: Jing Zhang <renyu.zj@...ux.alibaba.com>
---
.../pmu-events/arch/test/test_soc/sys/uncore.json | 8 ++++
tools/perf/tests/pmu-events.c | 55 ++++++++++++++++++++++
2 files changed, 63 insertions(+)
diff --git a/tools/perf/pmu-events/arch/test/test_soc/sys/uncore.json b/tools/perf/pmu-events/arch/test/test_soc/sys/uncore.json
index c7e7528..879a0ae 100644
--- a/tools/perf/pmu-events/arch/test/test_soc/sys/uncore.json
+++ b/tools/perf/pmu-events/arch/test/test_soc/sys/uncore.json
@@ -12,5 +12,13 @@
"EventName": "sys_ccn_pmu.read_cycles",
"Unit": "sys_ccn_pmu",
"Compat": "0x01"
+ },
+ {
+ "BriefDescription": "Counts total cache misses in first lookup result (high priority).",
+ "Type": "0x05",
+ "EventIdCode": "0x01",
+ "EventName": "sys_cmn_pmu.hnf_cache_miss",
+ "Unit": "arm_cmn",
+ "Compat": "434*;436*;43c*;43a01"
}
]
diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c
index 1dff863b..e227dcd 100644
--- a/tools/perf/tests/pmu-events.c
+++ b/tools/perf/tests/pmu-events.c
@@ -255,9 +255,24 @@ struct perf_pmu_test_pmu {
.matching_pmu = "uncore_sys_ccn_pmu",
};
+static const struct perf_pmu_test_event sys_cmn_pmu_hnf_cache_miss = {
+ .event = {
+ .name = "sys_cmn_pmu.hnf_cache_miss",
+ .event = "type=0x05,eventid=0x01",
+ .desc = "Counts total cache misses in first lookup result (high priority). Unit: uncore_arm_cmn ",
+ .topic = "uncore",
+ .pmu = "uncore_arm_cmn",
+ .compat = "434*;436*;43c*;43a01",
+ },
+ .alias_str = "type=0x5,eventid=0x1",
+ .alias_long_desc = "Counts total cache misses in first lookup result (high priority). Unit: uncore_arm_cmn ",
+ .matching_pmu = "uncore_arm_cmn_0",
+};
+
static const struct perf_pmu_test_event *sys_events[] = {
&sys_ddr_pmu_write_cycles,
&sys_ccn_pmu_read_cycles,
+ &sys_cmn_pmu_hnf_cache_miss,
NULL
};
@@ -699,6 +714,46 @@ static int __test_uncore_pmu_event_aliases(struct perf_pmu_test_pmu *test_pmu)
&sys_ccn_pmu_read_cycles,
},
},
+ {
+ .pmu = {
+ .name = (char *)"uncore_arm_cmn_0",
+ .is_uncore = 1,
+ .id = (char *)"43401",
+ },
+ .aliases = {
+ &sys_cmn_pmu_hnf_cache_miss,
+ },
+ },
+ {
+ .pmu = {
+ .name = (char *)"uncore_arm_cmn_0",
+ .is_uncore = 1,
+ .id = (char *)"43602",
+ },
+ .aliases = {
+ &sys_cmn_pmu_hnf_cache_miss,
+ },
+ },
+ {
+ .pmu = {
+ .name = (char *)"uncore_arm_cmn_1",
+ .is_uncore = 1,
+ .id = (char *)"43c03",
+ },
+ .aliases = {
+ &sys_cmn_pmu_hnf_cache_miss,
+ },
+ },
+ {
+ .pmu = {
+ .name = (char *)"uncore_arm_cmn_1",
+ .is_uncore = 1,
+ .id = (char *)"43a01",
+ },
+ .aliases = {
+ &sys_cmn_pmu_hnf_cache_miss,
+ },
+ }
};
/* Test that aliases generated are as expected */
--
1.8.3.1
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