linux-kernel - Re: [PATCH v5 4/5] perf jevents: Add support for Arm CMN PMU aliasing

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Message-ID: <01f793eb-6373-e6c0-a712-9e08ee3c91c8@oracle.com>
Date:   Fri, 28 Jul 2023 09:17:14 +0100
From:   John Garry <john.g.garry@...cle.com>
To:     Jing Zhang <renyu.zj@...ux.alibaba.com>,
        Ian Rogers <irogers@...gle.com>
Cc:     Will Deacon <will@...nel.org>, Mark Rutland <mark.rutland@....com>,
        Robin Murphy <robin.murphy@....com>,
        Ilkka Koskinen <ilkka@...amperecomputing.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-perf-users@...r.kernel.org, linux-doc@...r.kernel.org,
        Zhuo Song <zhuo.song@...ux.alibaba.com>,
        Shuai Xue <xueshuai@...ux.alibaba.com>
Subject: Re: [PATCH v5 4/5] perf jevents: Add support for Arm CMN PMU aliasing

On 28/07/2023 07:17, Jing Zhang wrote:
> Currently just add aliases for part of Arm CMN PMU events which are
> general and compatible for any SoC and CMN-ANY.
> 
> "Compat" value "434*;436*;43c*;43a*" means it is compatible with all

As mentioned in patch 1/5, a comma-separated list seems a better 
delimiter to me

> CMN600/CMN650/CMN700/Ci700.

It would be good if you could provide a link to where you got these 
events. I think that it is the publicly available CMN TRM document.

> 
> Signed-off-by: Jing Zhang<renyu.zj@...ux.alibaba.com>

Apart from comments, above:

Reviewed-by: John Garry <john.g.garry@...cle.com>