linux-kernel - Re: [PATCH 0/4] RISCV: Add kvm Sstc timer selftest

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Message-ID: <CAJve8o=GZnLLedT7TvCLvgd5Z3ZxJNfM6gG03Eyc+7krtMY--g@mail.gmail.com>
Date:   Fri, 28 Jul 2023 09:37:36 +0800
From:   Haibo Xu <xiaobo55x@...il.com>
To:     Sean Christopherson <seanjc@...gle.com>
Cc:     Haibo Xu <haibo1.xu@...el.com>, ajones@...tanamicro.com,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Shuah Khan <shuah@...nel.org>,
        Anup Patel <anup@...infault.org>,
        Atish Patra <atishp@...shpatra.org>,
        Vipin Sharma <vipinsh@...gle.com>,
        Colton Lewis <coltonlewis@...gle.com>,
        Marc Zyngier <maz@...nel.org>,
        Andrew Jones <andrew.jones@...ux.dev>,
        Vishal Annapurve <vannapurve@...gle.com>,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        kvm@...r.kernel.org, linux-kselftest@...r.kernel.org,
        kvm-riscv@...ts.infradead.org
Subject: Re: [PATCH 0/4] RISCV: Add kvm Sstc timer selftest

On Thu, Jul 27, 2023 at 11:14 PM Sean Christopherson <seanjc@...gle.com> wrote:
>
> On Thu, Jul 27, 2023, Haibo Xu wrote:
> > The sstc_timer selftest is used to validate Sstc timer functionality
> > in a guest, which sets up periodic timer interrupts and check the
> > basic interrupt status upon its receipt.
> >
> > This KVM selftest was ported from aarch64 arch_timer and tested
> > with Linux v6.5-rc3 on a Qemu riscv64 virt machine.
>
> Would it be possible to extract the ARM bits from arch_timer and make the bulk of
> the test common to ARM and RISC-V?  At a glance, there is quite a bit of copy+paste.

Sure, I will have a try to consolidate the common code for ARM and RISC-V in v2.

Thanks,
Haibo