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Message-ID: <20230731-upstream_csi-v8-8-fb7d3661c2c9@ti.com>
Date: Mon, 31 Jul 2023 13:59:26 +0530
From: Jai Luthra <j-luthra@...com>
To: Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Sakari Ailus <sakari.ailus@...ux.intel.com>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Tomi Valkeinen <tomi.valkeinen@...asonboard.com>
CC: <linux-media@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
Mauro Carvalho Chehab <mchehab+samsung@...nel.org>,
Maxime Ripard <mripard@...nel.org>,
<niklas.soderlund+renesas@...natech.se>,
Benoit Parrot <bparrot@...com>,
Vaishnav Achath <vaishnav.a@...com>,
Vignesh Raghavendra <vigneshr@...com>, <nm@...com>,
<devarsht@...com>, <j-luthra@...com>
Subject: [PATCH v8 08/16] media: cadence: csi2rx: Configure DPHY using link freq
From: Pratyush Yadav <p.yadav@...com>
Some platforms like TI's J721E can have the CSI2RX paired with an
external DPHY. Use the generic PHY framework to configure the DPHY with
the correct link frequency.
Signed-off-by: Pratyush Yadav <p.yadav@...com>
Co-authored-by: Jai Luthra <j-luthra@...com>
Signed-off-by: Jai Luthra <j-luthra@...com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@...asonboard.com>
---
v7->v8
- Drop original patch in-lieu of already merged
https://lore.kernel.org/linux-media/20230523085626.3295-5-jack.zhu@starfivetech.com/
- Add a new patch to configure DPHY using link_freq control from the
source
drivers/media/platform/cadence/cdns-csi2rx.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c
index 4f9654366485..2a80c66fb547 100644
--- a/drivers/media/platform/cadence/cdns-csi2rx.c
+++ b/drivers/media/platform/cadence/cdns-csi2rx.c
@@ -149,8 +149,33 @@ static void csi2rx_reset(struct csi2rx_priv *csi2rx)
static int csi2rx_configure_ext_dphy(struct csi2rx_priv *csi2rx)
{
union phy_configure_opts opts = { };
+ struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
+ struct v4l2_subdev_format sd_fmt = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .pad = CSI2RX_PAD_SINK,
+ .stream = 0,
+ };
+ const struct csi2rx_fmt *fmt;
+ s64 link_freq;
int ret;
+ ret = v4l2_subdev_call_state_active(&csi2rx->subdev, pad, get_fmt,
+ &sd_fmt);
+ if (ret < 0)
+ return ret;
+
+ fmt = csi2rx_get_fmt_by_code(sd_fmt.format.code);
+
+ link_freq = v4l2_get_link_freq(csi2rx->source_subdev->ctrl_handler,
+ fmt->bpp, 2 * csi2rx->num_lanes);
+ if (link_freq < 0)
+ return link_freq;
+
+ ret = phy_mipi_dphy_get_default_config_for_hsclk(link_freq,
+ csi2rx->num_lanes, cfg);
+ if (ret)
+ return ret;
+
ret = phy_power_on(csi2rx->dphy);
if (ret)
return ret;
--
2.41.0
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