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Message-ID: <ZMh4BW8a+82Ijzye@debian-scheme>
Date: Tue, 1 Aug 2023 11:12:05 +0800
From: Zhenyu Wang <zhenyuw@...ux.intel.com>
To: Yan Zhao <yan.y.zhao@...el.com>
Cc: intel-gfx@...ts.freedesktop.org,
intel-gvt-dev@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
zhi.a.wang@...el.com, zhenyuw@...ux.intel.com, kvm@...r.kernel.org
Subject: Re: [PATCH] drm/i915/gvt: Fix bug in getting msg length in AUX CH
registers handler
On 2023.07.31 19:20:33 +0800, Yan Zhao wrote:
> Msg length should be obtained from value written to AUX_CH_CTL register
> rather than from enum type of the register.
>
> Commit 0cad796a2269 ("drm/i915: Use REG_BIT() & co. for AUX CH registers")
> incorrectly calculates the msg_length from reg type and yields below
> warning in intel_gvt_i2c_handle_aux_ch_write():
> "i915 0000:00:02.0: drm_WARN_ON(msg_length != 4)".
>
> Fixes: 0cad796a2269 ("drm/i915: Use REG_BIT() & co. for AUX CH registers")
> Signed-off-by: Yan Zhao <yan.y.zhao@...el.com>
> ---
Thanks for the fix!
Reviewed-by: Zhenyu Wang <zhenyuw@...ux.intel.com>
> drivers/gpu/drm/i915/gvt/edid.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
> index 2a0438f12a14..af9afdb53c7f 100644
> --- a/drivers/gpu/drm/i915/gvt/edid.c
> +++ b/drivers/gpu/drm/i915/gvt/edid.c
> @@ -491,7 +491,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
> return;
> }
>
> - msg_length = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, reg);
> + msg_length = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, value);
>
> // check the msg in DATA register.
> msg = vgpu_vreg(vgpu, offset + 4);
> --
> 2.17.1
>
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