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Message-ID: <20230801-blatancy-chill-efee6e93f2e0@spud>
Date:   Tue, 1 Aug 2023 21:53:31 +0100
From:   Conor Dooley <conor@...nel.org>
To:     niravkumar.l.rabara@...el.com
Cc:     adrian.ho.yin.ng@...el.com, andrew@...n.ch, conor+dt@...nel.org,
        devicetree@...r.kernel.org, dinguyen@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, mturquette@...libre.com,
        netdev@...r.kernel.org, p.zabel@...gutronix.de,
        richardcochran@...il.com, robh+dt@...nel.org, sboyd@...nel.org,
        wen.ping.teh@...el.com
Subject: Re: [PATCH v2 1/5] dt-bindings: intel: Add Intel Agilex5 compatible

On Tue, Aug 01, 2023 at 09:02:30AM +0800, niravkumar.l.rabara@...el.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>
> 
> Agilex5 is a new SoCFPGA in Intel Agilex SoCFPGA Family,
> include compatible string for Agilex5 SoCFPGA board.
> 
> Reviewed-by: Dinh Nguyen <dinguyen@...nel.org>
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>

Acked-by: Conor Dooley <conor.dooley@...rochip.com>

Cheers,
Conor.

> ---
>  Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> index 4b4dcf551eb6..2ee0c740eb56 100644
> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> @@ -21,6 +21,11 @@ properties:
>                - intel,socfpga-agilex-n6000
>                - intel,socfpga-agilex-socdk
>            - const: intel,socfpga-agilex
> +      - description: Agilex5 boards
> +        items:
> +          - enum:
> +              - intel,socfpga-agilex5-socdk
> +          - const: intel,socfpga-agilex5
>  
>  additionalProperties: true
>  
> -- 
> 2.25.1
> 

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