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Message-ID: <CAMhs-H9RpyCTcrRjtALg_aqGR7cmrz_ufQdVYm=WSEgUObpxKA@mail.gmail.com>
Date: Tue, 1 Aug 2023 08:33:45 +0200
From: Sergio Paracuellos <sergio.paracuellos@...il.com>
To: Rafał Miłecki <zajec5@...il.com>
Cc: Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Arınç ÜNAL <arinc.unal@...nc9.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-mips@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Rafał Miłecki <rafal@...ecki.pl>
Subject: Re: [PATCH] mips: dts: ralink: reorder MT7621 clocks in Ethernet block
On Sat, Jul 29, 2023 at 1:04 PM Rafał Miłecki <zajec5@...il.com> wrote:
>
> From: Rafał Miłecki <rafal@...ecki.pl>
>
> Use order as specified in the binding (first "ethif" then "fe").
>
> This fixes:
> arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dtb: ethernet@...00000: clock-names:0: 'ethif' was expected
> From schema: Documentation/devicetree/bindings/net/mediatek,net.yaml
> arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dtb: ethernet@...00000: clock-names:1: 'fe' was expected
> From schema: Documentation/devicetree/bindings/net/mediatek,net.yaml
>
> Fixes: 7a6ee0bbab25 ("mips: dts: ralink: add MT7621 SoC")
> Signed-off-by: Rafał Miłecki <rafal@...ecki.pl>
> ---
> arch/mips/boot/dts/ralink/mt7621.dtsi | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
Acked-by: Sergio Paracuellos <sergio.paracuellos@...il.com>
Thanks,
Sergio Paracuellos
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