linux-kernel - RE: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock manager

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Date:   Wed, 2 Aug 2023 07:14:32 +0000
From:   "Rabara, Niravkumar L" <niravkumar.l.rabara@...el.com>
To:     Conor Dooley <conor.dooley@...rochip.com>
CC:     "Ng, Adrian Ho Yin" <adrian.ho.yin.ng@...el.com>,
        "andrew@...n.ch" <andrew@...n.ch>,
        "conor+dt@...nel.org" <conor+dt@...nel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "dinguyen@...nel.org" <dinguyen@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Turquette, Mike" <mturquette@...libre.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
        "richardcochran@...il.com" <richardcochran@...il.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "sboyd@...nel.org" <sboyd@...nel.org>,
        "wen.ping.teh@...el.com" <wen.ping.teh@...el.com>
Subject: RE: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock
 manager



> -----Original Message-----
> From: Conor Dooley <conor.dooley@...rochip.com>
> Sent: Wednesday, 2 August, 2023 3:02 PM
> To: Rabara, Niravkumar L <niravkumar.l.rabara@...el.com>
> Cc: Ng, Adrian Ho Yin <adrian.ho.yin.ng@...el.com>; andrew@...n.ch;
> conor+dt@...nel.org; devicetree@...r.kernel.org; dinguyen@...nel.org;
> krzysztof.kozlowski+dt@...aro.org; linux-clk@...r.kernel.org; linux-
> kernel@...r.kernel.org; Turquette, Mike <mturquette@...libre.com>;
> netdev@...r.kernel.org; p.zabel@...gutronix.de;
> richardcochran@...il.com; robh+dt@...nel.org; sboyd@...nel.org;
> wen.ping.teh@...el.com
> Subject: Re: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock
> manager
> 
> On Wed, Aug 02, 2023 at 10:58:42AM +0800, niravkumar.l.rabara@...el.com
> wrote:
> > From: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>
> >
> > Add clock ID definitions for Intel Agilex5 SoCFPGA.
> > The registers in Agilex5 handling the clock is named as clock manager.
> >
> > Signed-off-by: Teh Wen Ping <wen.ping.teh@...el.com>
> > Reviewed-by: Dinh Nguyen <dinguyen@...nel.org>
> > Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
> > Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>
> 
> Damn, I was too late - you already sent a v3 :/
> 
> However, there only seems to be a v3 of this one patch and it was sent in
> reply to the v2 series? The normal thing to do is resend the entire series, not
> just one patch, as a new thread. Not using a new thread may make it harder
> to apply & will also bury the email in people's mailboxes that use things like
> mutt. A single patch as a reply is also confusing, as the rest of the v3 looks like
> it is missing!
> 
> Thanks,
> Conor.

Sorry I made a mistake. 
Should I send out entire series with PATCH v3 subject? Or should I wait for review comment on remaining patches and then send entire series with rework and  subject prefix PATCH v3? 

Thanks,
Nirav