linux-kernel - [RESEND PATCH v3 2/2] ufs: poll HCS.UCRDY before issuing a UIC command

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Message-Id: <9c7ccbfb8fe05c29ab3e31d9cd14e6b91065b8b0.1690939662.git.kwmad.kim@samsung.com>
Date:   Wed,  2 Aug 2023 10:28:33 +0900
From:   Kiwoong Kim <kwmad.kim@...sung.com>
To:     linux-scsi@...r.kernel.org, linux-kernel@...r.kernel.org,
        alim.akhtar@...sung.com, avri.altman@....com, bvanassche@....org,
        jejb@...ux.ibm.com, martin.petersen@...cle.com, beanhuo@...ron.com,
        adrian.hunter@...el.com, sc.suh@...sung.com, hy50.seo@...sung.com,
        sh425.lee@...sung.com, kwangwon.min@...sung.com,
        junwoo80.lee@...sung.com, wkon.kim@...sung.com
Cc:     Kiwoong Kim <kwmad.kim@...sung.com>
Subject: [RESEND PATCH v3 2/2] ufs: poll HCS.UCRDY before issuing a UIC
 command

With auto hibern8 enabled, UIC could be working
for a while to process a hibern8 operation and HCI
reports UIC not ready for a short term through HCS.UCRDY.
And UFS driver can't recognize the operation.
UFSHCI spec specifies UCRDY like this:
whether the host controller is ready to process UIC COMMAND

The 'ready' could be seen as many different meanings. If the meaning
includes not processing any request from HCI, processing a hibern8
operation can be 'not ready'. In this situation, the driver needs to
wait until the operations is completed.

Signed-off-by: Kiwoong Kim <kwmad.kim@...sung.com>
---
 drivers/ufs/core/ufshcd.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index a89d39a..10ccc85 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -22,6 +22,7 @@
 #include <linux/module.h>
 #include <linux/regulator/consumer.h>
 #include <linux/sched/clock.h>
+#include <linux/iopoll.h>
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_dbg.h>
 #include <scsi/scsi_driver.h>
@@ -2365,7 +2366,11 @@ static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
  */
 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
 {
-	return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY;
+	u32 val;
+	int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY,
+				    500, UIC_CMD_TIMEOUT * 1000, false, hba,
+				    REG_CONTROLLER_STATUS);
+	return ret == 0 ? true : false;
 }
 
 /**
-- 
2.7.4