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Message-ID: <AS8PR04MB86762F0D36E7BC41D79CEA2F8C0BA@AS8PR04MB8676.eurprd04.prod.outlook.com>
Date:   Wed, 2 Aug 2023 14:08:54 +0000
From:   Hongxing Zhu <hongxing.zhu@....com>
To:     Ahmad Fatoum <a.fatoum@...gutronix.de>,
        "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "lpieralisi@...nel.org" <lpieralisi@...nel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>
CC:     "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        dl-linux-imx <linux-imx@....com>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: RE: [PATCH 0/9] Add legacy i.MX PCIe EP mode supports

Hi Ahmad:

Thanks for your concerns.
> -----Original Message-----
> From: Ahmad Fatoum <a.fatoum@...gutronix.de>
> Sent: 2023年8月2日 14:52
> To: Hongxing Zhu <hongxing.zhu@....com>; l.stach@...gutronix.de;
> shawnguo@...nel.org; lpieralisi@...nel.org; robh+dt@...nel.org;
> krzysztof.kozlowski+dt@...aro.org
> Cc: devicetree@...r.kernel.org; linux-pci@...r.kernel.org;
> linux-kernel@...r.kernel.org; dl-linux-imx <linux-imx@....com>;
> kernel@...gutronix.de; linux-arm-kernel@...ts.infradead.org
> Subject: Re: [PATCH 0/9] Add legacy i.MX PCIe EP mode supports
>
> Hello Richard,
>
> On 02.08.23 08:06, Richard Zhu wrote:
> > Add legacy 32bit i.MX PCIe EP mode support
> >
> > The PCI controller contained in i.MX6/7 legacy SOCs is one dual mode
> > PCIe controller, and can work either as RC or EP.
> >
> > This series add i.MX6/7 PCIe EP mode supports. And had been verified
> > on i.MX6 sabresd and i.MX7 SDB boards.
> >
> > In the verification, one board PCIe is used as RC, the other one is
> > used as EP.
> > Use the cross TX/RX differential cable connect the two PCIe ports of
> > these two boards.
> >
> > +-----------+                +------------+
> > |   PCIe TX |<-------------->|PCIe RX     |
> > |           |                |            |
> > |    Board  |                |    Board   |
> > |           |                |            |
> > |   PCIe RX |<-------------->|PCIe TX     |
> > +-----------+                +------------+
>
> I am curious what software you are running on both sides to test?
> Do you use CONFIG_PCI_EPF_TEST? What do you run on RC side?
Yes, it is.
Beside PCI_EPF_TEST, the CONFIG_PCI_ENDPOINT_TEST is used too.
And the pcitest program is used on RC side to verify the MSI and data IO tests features.

Best Regards
Richard Zhu
>
> Thanks,
> Ahmad
>
> >
> > [PATCH 1/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6Q and i.MX6QP PCIe
> > [PATCH 2/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6SX PCIe EP [PATCH
> > 3/9] dt-bindings: PCI: fsl,imx6q: Add i.MX7D PCIe EP [PATCH 4/9] arm:
> > dts: nxp: Add i.MX6QDL and i.MX6QP PCIe EP supports [PATCH 5/9] arm:
> > dts: nxp: Add i.MX6SX PCIe EP support [PATCH 6/9] arm: dts: nxp: Add
> > i.MX7D PCIe EP support [PATCH 7/9] PCI: imx6: Add i.MX6Q and i.MX6QP
> > PCIe EP supports [PATCH 8/9] PCI: imx6: Add i.MX6SX PCIe EP support
> > [PATCH 9/9] PCI: imx6: Add i.MX7D PCIe EP support
> >
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 50
> +++++++++++++++++++++++++++++++++++++++++----
> > arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi                       | 14
> +++++++++++++
> > arch/arm/boot/dts/nxp/imx/imx6qp.dtsi                        |  4
> ++++
> > arch/arm/boot/dts/nxp/imx/imx6sx.dtsi                        | 17
> +++++++++++++++
> > arch/arm/boot/dts/nxp/imx/imx7d.dtsi                         | 27
> ++++++++++++++++++++++++
> > drivers/pci/controller/dwc/pci-imx6.c                        | 93
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++-
> > 6 files changed, 200 insertions(+), 5 deletions(-)
> >
> >
> >
>
> --
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