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Message-Id: <20230803175916.3174453-14-sunilvl@ventanamicro.com>
Date: Thu, 3 Aug 2023 23:29:08 +0530
From: Sunil V L <sunilvl@...tanamicro.com>
To: linux-doc@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-acpi@...r.kernel.org, linux-pci@...r.kernel.org
Cc: Jonathan Corbet <corbet@....net>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
"Rafael J . Wysocki" <rafael@...nel.org>,
Len Brown <lenb@...nel.org>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
Daniel Scally <djrscally@...il.com>,
Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
Sakari Ailus <sakari.ailus@...ux.intel.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Anup Patel <anup@...infault.org>,
Marc Zyngier <maz@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Robert Moore <robert.moore@...el.com>,
Haibo Xu <haibo1.xu@...el.com>,
Andrew Jones <ajones@...tanamicro.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Atish Kumar Patra <atishp@...osinc.com>,
Sunil V L <sunilvl@...tanamicro.com>
Subject: [RFC PATCH v1 13/21] irqchip/riscv-imsic-early: Add ACPI support
Add support to probe the IMSIC early driver on ACPI
based RISC-V platforms.
Signed-off-by: Sunil V L <sunilvl@...tanamicro.com>
---
arch/riscv/include/asm/acpi.h | 6 +++
drivers/acpi/riscv/irqchip.c | 57 +++++++++++++++++++++++++
drivers/irqchip/irq-riscv-imsic-early.c | 28 ++++++++++++
drivers/irqchip/irq-riscv-imsic-state.c | 33 +++++++++++---
4 files changed, 119 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h
index 0ac2df2dd194..6dde3d63dc0e 100644
--- a/arch/riscv/include/asm/acpi.h
+++ b/arch/riscv/include/asm/acpi.h
@@ -69,6 +69,8 @@ static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; }
int acpi_get_cbo_block_size(struct acpi_table_header *table, unsigned int cpu, u32 *cbom_size,
u32 *cboz_size, u32 *cbop_size);
struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc);
+struct fwnode_handle *acpi_imsic_create_fwnode(struct acpi_madt_imsic *imsic);
+struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev);
#else
static inline void acpi_init_rintc_map(void) { }
static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu)
@@ -89,6 +91,10 @@ static inline int acpi_get_cbo_block_size(struct acpi_table_header *table,
return -EINVAL;
}
+static inline struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev)
+{
+ return NULL;
+}
#endif /* CONFIG_ACPI */
#endif /*_ASM_ACPI_H*/
diff --git a/drivers/acpi/riscv/irqchip.c b/drivers/acpi/riscv/irqchip.c
index 36f066a2cad5..6e15d45cb229 100644
--- a/drivers/acpi/riscv/irqchip.c
+++ b/drivers/acpi/riscv/irqchip.c
@@ -18,6 +18,8 @@ struct riscv_irqchip_list {
LIST_HEAD(rintc_list);
+static struct fwnode_handle *imsic_acpi_fwnode;
+
struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc)
{
struct property_entry props[6] = {};
@@ -44,3 +46,58 @@ struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *r
return fwnode;
}
+
+static struct fwnode_handle *acpi_imsic_get_rintc_fwnode(u32 idx)
+{
+ struct riscv_irqchip_list *rintc_element;
+ struct fwnode_handle *fwnode;
+ struct list_head *i, *tmp;
+ unsigned int j = 0;
+
+ list_for_each_safe(i, tmp, &rintc_list) {
+ rintc_element = list_entry(i, struct riscv_irqchip_list, list);
+ fwnode = rintc_element->fwnode;
+
+ if (j == idx)
+ return fwnode;
+
+ j++;
+ }
+
+ return NULL;
+}
+
+struct fwnode_handle *acpi_imsic_create_fwnode(struct acpi_madt_imsic *imsic)
+{
+ struct property_entry props[8] = {};
+ struct software_node_ref_args *refs;
+ struct fwnode_handle *parent_fwnode;
+ unsigned int nr_rintc, i;
+
+ props[0] = PROPERTY_ENTRY_U32("riscv,guest-index-bits", imsic->guest_index_bits);
+ props[1] = PROPERTY_ENTRY_U32("riscv,hart-index-bits", imsic->hart_index_bits);
+ props[2] = PROPERTY_ENTRY_U32("riscv,group-index-bits", imsic->group_index_bits);
+ props[3] = PROPERTY_ENTRY_U32("riscv,group-index-shift", imsic->group_index_shift);
+ props[4] = PROPERTY_ENTRY_U32("riscv,num-ids", imsic->num_ids);
+ props[5] = PROPERTY_ENTRY_U32("riscv,num-guest-ids", imsic->num_guest_ids);
+
+ nr_rintc = list_count_nodes(&rintc_list);
+ refs = kcalloc(nr_rintc, sizeof(*refs), GFP_KERNEL);
+ if (!refs)
+ return NULL;
+
+ for (i = 0; i < nr_rintc; i++) {
+ parent_fwnode = acpi_imsic_get_rintc_fwnode(i);
+ refs[i] = SOFTWARE_NODE_REFERENCE(to_software_node(parent_fwnode), RV_IRQ_EXT);
+ }
+ props[6] = PROPERTY_ENTRY_REF_ARRAY_LEN("interrupts-extended", refs, nr_rintc);
+
+ imsic_acpi_fwnode = fwnode_create_software_node_early(props, NULL);
+
+ return imsic_acpi_fwnode;
+}
+
+struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev)
+{
+ return imsic_acpi_fwnode;
+}
diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c
index 1de89ce1ec2f..93f4d748ca6d 100644
--- a/drivers/irqchip/irq-riscv-imsic-early.c
+++ b/drivers/irqchip/irq-riscv-imsic-early.c
@@ -12,6 +12,7 @@
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/module.h>
+#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
@@ -256,3 +257,30 @@ static int __init imsic_early_dt_init(struct device_node *node,
return 0;
}
IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init);
+
+#ifdef CONFIG_ACPI
+static int __init imsic_early_acpi_init(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct fwnode_handle *fwnode;
+ int rc;
+
+ /*
+ * There should be only one IMSIC node.
+ */
+ fwnode = acpi_imsic_create_fwnode((struct acpi_madt_imsic *)header);
+ if (!fwnode) {
+ pr_err("unable to create IMSIC FW node\n");
+ return -ENOMEM;
+ }
+
+ rc = imsic_early_probe(fwnode);
+ if (!rc)
+ pci_msi_register_fwnode_provider(&acpi_riscv_get_msi_fwnode);
+
+ return rc;
+}
+
+IRQCHIP_ACPI_DECLARE(riscv_imsic, ACPI_MADT_TYPE_IMSIC,
+ NULL, 1, imsic_early_acpi_init);
+#endif
diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c
index 412b5b919dcc..d0e09e51e8ae 100644
--- a/drivers/irqchip/irq-riscv-imsic-state.c
+++ b/drivers/irqchip/irq-riscv-imsic-state.c
@@ -225,15 +225,38 @@ static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode,
return riscv_get_intc_hartid(parent.fwnode, hartid);
}
+static int __init imsic_acpi_get_mmio_resource(struct fwnode_handle *fwnode,
+ u32 index, struct resource *res)
+{
+ int rc;
+ struct fwnode_reference_args parent;
+ u64 base;
+ u32 size;
+
+ rc = fwnode_property_get_reference_args(fwnode,
+ "interrupts-extended", NULL,
+ 0, index, &parent);
+ if (rc)
+ return rc;
+
+ rc = fwnode_property_read_u64_array(parent.fwnode, "riscv,imsic-addr",
+ &base, 1);
+ rc = fwnode_property_read_u32_array(parent.fwnode, "riscv,imsic-size",
+ &size, 1);
+ if (!rc) {
+ res->start = base;
+ res->end = res->start + size - 1;
+ }
+
+ return 0;
+}
+
static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode,
u32 index, struct resource *res)
{
- /*
- * Currently, only OF fwnode is support so extend this function
- * for other types of fwnode for ACPI support.
- */
if (!is_of_node(fwnode))
- return -EINVAL;
+ return imsic_acpi_get_mmio_resource(fwnode, index, res);
+
return of_address_to_resource(to_of_node(fwnode), index, res);
}
--
2.39.2
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