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Message-ID: <2151031.irdbgypaU6@jernej-laptop>
Date: Thu, 03 Aug 2023 22:54:08 +0200
From: Jernej Škrabec <jernej.skrabec@...il.com>
To: linux-sunxi@...ts.linux.dev, John Watts <contact@...kia.org>
Cc: John Watts <contact@...kia.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Chen-Yu Tsai <wens@...e.org>,
Samuel Holland <samuel@...lland.org>,
Cristian Ciocaltea <cristian.ciocaltea@...labora.com>,
Maksim Kiselev <bigunclemax@...il.com>,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] riscv: dts: allwinner: d1: Specify default CAN pins
Dne ponedeljek, 31. julij 2023 ob 04:36:59 CEST je John Watts napisal(a):
> There are only one set of CAN pins available on these chips.
> Specify these as the default to avoid redundancy in board device trees.
>
> Signed-off-by: John Watts <contact@...kia.org>
> ---
> arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index
> 4086c0cc0f9d..b27c3fc13b0d 100644
> --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> @@ -898,6 +898,8 @@ can0: can@...4000 {
> interrupts = <SOC_PERIPHERAL_IRQ(21)
IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_CAN0>;
> resets = <&ccu RST_BUS_CAN0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&can0_pins>;
> status = "disabled";
> };
>
> @@ -907,6 +909,8 @@ can1: can@...4400 {
> interrupts = <SOC_PERIPHERAL_IRQ(22)
IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_CAN1>;
> resets = <&ccu RST_BUS_CAN1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&can1_pins>;
> status = "disabled";
> };
> };
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