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Message-ID: <BN9PR11MB527649D7E79E29291DA1A5538C08A@BN9PR11MB5276.namprd11.prod.outlook.com>
Date:   Thu, 3 Aug 2023 00:44:03 +0000
From:   "Tian, Kevin" <kevin.tian@...el.com>
To:     Jason Gunthorpe <jgg@...pe.ca>, Lu Baolu <baolu.lu@...ux.intel.com>
CC:     Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
        "Robin Murphy" <robin.murphy@....com>,
        Jean-Philippe Brucker <jean-philippe@...aro.org>,
        Nicolin Chen <nicolinc@...dia.com>,
        "Liu, Yi L" <yi.l.liu@...el.com>,
        Jacob Pan <jacob.jun.pan@...ux.intel.com>,
        "iommu@...ts.linux.dev" <iommu@...ts.linux.dev>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 0/2] iommu: Make pasid array per device

> From: Jason Gunthorpe <jgg@...pe.ca>
> Sent: Wednesday, August 2, 2023 10:16 PM
> 
> On Tue, Aug 01, 2023 at 02:31:23PM +0800, Lu Baolu wrote:
> > The PCI PASID enabling interface guarantees that the address space used
> > by each PASID is unique. This is achieved by checking that the PCI ACS
> > path is enabled for the device. If the path is not enabled, then the
> > PASID feature cannot be used.
> >
> >     if (!pci_acs_path_enabled(pdev, NULL, PCI_ACS_RR | PCI_ACS_UF))
> >             return -EINVAL;
> >
> > The PASID array is not an attribute of the IOMMU group. It is more
> > natural to store the PASID array in the per-device IOMMU data. This
> > makes the code clearer and easier to understand. No functional changes
> > are intended.
> 
> Is there a reason to do this?
> 
> *PCI* requires the ACS/etc because PCI kind of messed up how switches
> handled PASID so PASID doesn't work otherwise.
> 
> But there is nothing that says other bus type can't have working
> (non-PCI) PASID and still have device isolation issues.
> 
> So unless there is a really strong reason to do this we should keep
> the PASID list in the group just like the domain.
> 

this comes from the consensus in [1].

[1] https://lore.kernel.org/linux-iommu/ZAcyEzN4102gPsWC@nvidia.com/

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