linux-kernel - Re: [PATCH v8 09/16] media: cadence: csi2rx: Soft reset the streams before starting capture

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Message-ID: <colvp5wmyedwoxchnifpaqipa7bv7g7hooxev3j5agvnuekfve@3cpxre6uoqbm>
Date:   Thu, 3 Aug 2023 16:49:57 +0530
From:   Jai Luthra <j-luthra@...com>
To:     Tomi Valkeinen <tomi.valkeinen@...asonboard.com>
CC:     Mauro Carvalho Chehab <mchehab@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Sakari Ailus <sakari.ailus@...ux.intel.com>,
        Laurent Pinchart <laurent.pinchart@...asonboard.com>,
        <linux-media@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        Mauro Carvalho Chehab <mchehab+samsung@...nel.org>,
        Maxime Ripard <mripard@...nel.org>,
        <niklas.soderlund+renesas@...natech.se>,
        Benoit Parrot <bparrot@...com>,
        Vaishnav Achath <vaishnav.a@...com>,
        Vignesh Raghavendra <vigneshr@...com>, <nm@...com>,
        <devarsht@...com>
Subject: Re: [PATCH v8 09/16] media: cadence: csi2rx: Soft reset the streams
 before starting capture

On Aug 01, 2023 at 17:16:41 +0300, Tomi Valkeinen wrote:
> On 31/07/2023 11:29, Jai Luthra wrote:
> > From: Pratyush Yadav <p.yadav@...com>
> > 
> > This resets the stream state machines and FIFOs, giving them a clean
> > slate. On J721E if the streams are not reset before starting the
> > capture, the captured frame gets wrapped around vertically on every run
> > after the first.
> > 
> > Signed-off-by: Pratyush Yadav <p.yadav@...com>
> > Signed-off-by: Jai Luthra <j-luthra@...com>
> > Reviewed-by: Laurent Pinchart <laurent.pinchart@...asonboard.com>
> > ---
> > v7->v8: No change
> > 
> >   drivers/media/platform/cadence/cdns-csi2rx.c | 11 +++++++++++
> >   1 file changed, 11 insertions(+)
> > 
> > diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c
> > index 2a80c66fb547..30cdc260b46a 100644
> > --- a/drivers/media/platform/cadence/cdns-csi2rx.c
> > +++ b/drivers/media/platform/cadence/cdns-csi2rx.c
> > @@ -40,6 +40,7 @@
> >   #define CSI2RX_STREAM_BASE(n)		(((n) + 1) * 0x100)
> >   #define CSI2RX_STREAM_CTRL_REG(n)		(CSI2RX_STREAM_BASE(n) + 0x000)
> > +#define CSI2RX_STREAM_CTRL_SOFT_RST			BIT(4)
> >   #define CSI2RX_STREAM_CTRL_START			BIT(0)
> >   #define CSI2RX_STREAM_DATA_CFG_REG(n)		(CSI2RX_STREAM_BASE(n) + 0x008)
> > @@ -138,12 +139,22 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev)
> >   static void csi2rx_reset(struct csi2rx_priv *csi2rx)
> >   {
> > +	unsigned int i;
> > +
> >   	writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT,
> >   	       csi2rx->base + CSI2RX_SOFT_RESET_REG);
> >   	udelay(10);
> >   	writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG);
> > +
> > +	/* Reset individual streams. */
> > +	for (i = 0; i < csi2rx->max_streams; i++) {
> > +		writel(CSI2RX_STREAM_CTRL_SOFT_RST,
> > +		       csi2rx->base + CSI2RX_STREAM_CTRL_REG(i));
> > +		usleep_range(10, 20);
> > +		writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i));
> > +	}
> 
> Do you have to do it like this? Or would it be fine to set the reset bit for
> all stream regs, then sleep, then clear the reset bit from all stream regs?
> Or going even further, can you set the CSI2RX_SOFT_RESET_REG and all
> CSI2RX_STREAM_CTRL_REG regs, then sleep, and then clear them all?

You're right I think that should work, and would be much cleaner. Will 
fix.

> 
>  Tomi
> 

-- 
Thanks,
Jai

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