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Message-ID: <20230803115016.4266-1-thippeswamy.havalige@amd.com>
Date: Thu, 3 Aug 2023 17:20:16 +0530
From: Thippeswamy Havalige <thippeswamy.havalige@....com>
To: <linux-kernel@...r.kernel.org>, <robh+dt@...nel.org>,
<bhelgaas@...gle.com>, <linux-pci@...r.kernel.org>
CC: <krzysztof.kozlowski@...aro.org>, <lpieralisi@...nel.org>,
<bharat.kumar.gogada@....com>, <michal.simek@....com>,
<linux-arm-kernel@...ts.infradead.org>,
Thippeswamy Havalige <thippeswamy.havalige@....com>
Subject: [PATCH] PCI: xilinx-nwl: Remove unnecessary code and updating ecam default value.
Remove reduntant code.
Change NWL_ECAM_VALUE_DEFAULT to 16 to support maximum 256 buses.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@....com>
---
drivers/pci/controller/pcie-xilinx-nwl.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 176686b..6d40543 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -126,7 +126,7 @@
#define E_ECAM_CR_ENABLE BIT(0)
#define E_ECAM_SIZE_LOC GENMASK(20, 16)
#define E_ECAM_SIZE_SHIFT 16
-#define NWL_ECAM_VALUE_DEFAULT 12
+#define NWL_ECAM_VALUE_DEFAULT 16
#define CFG_DMA_REG_BAR GENMASK(2, 0)
#define CFG_PCIE_CACHE GENMASK(7, 0)
@@ -683,15 +683,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
E_ECAM_BASE_HI);
- /* Get bus range */
- ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
- pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
- /* Write primary, secondary and subordinate bus numbers */
- ecam_val = first_busno;
- ecam_val |= (first_busno + 1) << 8;
- ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
- writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
-
if (nwl_pcie_link_up(pcie))
dev_info(dev, "Link is UP\n");
else
--
1.8.3.1
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