linux-kernel - Re: [PATCH v9 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node

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Message-ID: <db05ca30-c31e-1c4a-95b5-ae15b85ce3bc@ti.com>
Date:   Sat, 5 Aug 2023 01:03:02 +0530
From:   Aradhya Bhatia <a-bhatia1@...com>
To:     Jayesh Choudhary <j-choudhary@...com>, <nm@...com>,
        <vigneshr@...com>, <afd@...com>, <rogerq@...nel.org>
CC:     <s-vadapalli@...com>, <kristo@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <r-ravikumar@...com>, <sabiya.d@...com>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v9 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and
 DP-bridge node



On 03-Aug-23 13:34, Jayesh Choudhary wrote:
> From: Rahul T R <r-ravikumar@...com>
> 
> Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
> same as DSS IP in J721E, so same compatible is being used.
> The DP is Cadence MHDP8546.
DP-bridge

> 
> Signed-off-by: Rahul T R <r-ravikumar@...com>
> [j-choudhary@...com: move dss & mhdp node together in main, fix dss node]
> Signed-off-by: Jayesh Choudhary <j-choudhary@...com>

Given that you make appropriate changes with properties in this patch,
wrt patches 4/5 and 5/5,

Reviewed-by: Aradhya Bhatia <a-bhatia1@...com>

> ---
>  arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 63 ++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 446d7efa715f..824312b9ef9f 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -1741,4 +1741,67 @@ c71_3: dsp@...00000 {
>  		resets = <&k3_reset 40 1>;
>  		firmware-name = "j784s4-c71_3-fw";
>  	};
> +
> +	mhdp: bridge@...0000 {
> +		compatible = "ti,j721e-mhdp8546";
> +		reg = <0x0 0xa000000 0x0 0x30a00>,
> +		      <0x0 0x4f40000 0x0 0x20>;
> +		reg-names = "mhdptx", "j721e-intg";
> +		clocks = <&k3_clks 217 11>;
> +		interrupt-parent = <&gic500>;
> +		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
> +		power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
> +		status = "disabled";
> +
> +		dp0_ports: ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +
> +	dss: dss@...0000 {
> +		compatible = "ti,j721e-dss";
> +		reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
> +		      <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
> +		      <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
> +		      <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
> +		      <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
> +		      <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
> +		      <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
> +		      <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
> +		      <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
> +		      <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
> +		      <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
> +		      <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
> +		      <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
> +		      <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
> +		      <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
> +		      <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
> +		      <0x00 0x04af0000 0x00 0x10000>; /* wb */
> +		reg-names = "common_m", "common_s0",
> +			    "common_s1", "common_s2",
> +			    "vidl1", "vidl2","vid1","vid2",
> +			    "ovr1", "ovr2", "ovr3", "ovr4",
> +			    "vp1", "vp2", "vp3", "vp4",
> +			    "wb";
> +		clocks = <&k3_clks 218 0>,
> +			 <&k3_clks 218 2>,
> +			 <&k3_clks 218 5>,
> +			 <&k3_clks 218 14>,
> +			 <&k3_clks 218 18>;
> +		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
> +		power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
> +		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "common_m",
> +				  "common_s0",
> +				  "common_s1",
> +				  "common_s2";
> +		status = "disabled";
> +
> +		dss_ports: ports {
> +		};
> +	};
>  };