linux-kernel - Re: (subset) [PATCH v6 0/3] Add initialization of clock for StarFive JH7110 SoC

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Message-Id: <20230805-imaginary-paramedic-deb52367e36a@spud>
Date:   Sat,  5 Aug 2023 10:09:04 +0100
From:   Conor Dooley <conor@...nel.org>
To:     devicetree@...r.kernel.org, linux-spi@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        William Qiu <william.qiu@...rfivetech.com>
Cc:     conor@...nel.org, Conor Dooley <conor.dooley@...rochip.com>,
        Mark Brown <broonie@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Emil Renner Berthing <kernel@...il.dk>,
        Ziv Xu <ziv.xu@...rfivetech.com>
Subject: Re: (subset) [PATCH v6 0/3] Add initialization of clock for StarFive JH7110 SoC

From: Conor Dooley <conor.dooley@...rochip.com>

On Fri, 04 Aug 2023 10:02:51 +0800, William Qiu wrote:
> This patchset adds initial rudimentary support for the StarFive
> Quad SPI controller driver. And this driver will be used in
> StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB
> clocks changed from the default ON state to the default OFF state,
> so these clocks need to be enabled in the driver.At the same time,
> dts patch is added to this series.
> 
> [...]

Applied to riscv-dt-for-next, thanks!

[3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
      https://git.kernel.org/conor/c/fc3d49f970d2

Thanks,
Conor.