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Message-ID: <3570165.R56niFO833@jernej-laptop>
Date:   Sun, 06 Aug 2023 15:42:34 +0200
From:   Jernej Škrabec <jernej.skrabec@...il.com>
To:     Maxime Ripard <mripard@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
        Samuel Holland <samuel@...lland.org>,
        Andre Przywara <andre.przywara@....com>,
        Roman Beranek <me@...y.cz>, Frank Oltmanns <frank@...manns.dev>
Cc:     linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org,
        Frank Oltmanns <frank@...manns.dev>
Subject: Re: [PATCH v5 09/11] clk: sunxi-ng: div: Support finding closest rate

Dne nedelja, 06. avgust 2023 ob 15:06:54 CEST je Frank Oltmanns napisal(a):
> Add initalization macros for divisor clocks with mux
> (SUNXI_CCU_M_WITH_MUX) to support finding the closest rate. This clock
> type requires the appropriate flags to be set in the .common structure
> (for the mux part of the clock) and the .div part.
> 
> Acked-by: Maxime Ripard <mripard@...nel.org>
> Signed-off-by: Frank Oltmanns <frank@...manns.dev>

Reviewed-by: Jernej Skrabec <jernej.skrabec@...il.com>

Best regards,
Jernej

> ---
>  drivers/clk/sunxi-ng/ccu_div.h | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
> index 948e2b0c0c3b..90d49ee8e0cc 100644
> --- a/drivers/clk/sunxi-ng/ccu_div.h
> +++ b/drivers/clk/sunxi-ng/ccu_div.h
> @@ -143,6 +143,26 @@ struct ccu_div {
>  		},					
		\
>  	}
> 
> +#define SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(_struct, _name,		
\
> +						_parents, 
_table,	\
> +						_reg,		
	\
> +						_mshift, 
_mwidth,	\
> +						_muxshift, 
_muxwidth,	\
> +						_gate, 
_flags)		\
> +	struct ccu_div _struct = {					
\
> +		.enable	= _gate,				
	\
> +		.div	= _SUNXI_CCU_DIV_FLAGS(_mshift, _mwidth, 
CLK_DIVIDER_ROUND_CLOSEST),
> \ +		.mux	= _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, 
_table), \
> +		.common	= {					
	\
> +			.reg		= _reg,			
	\
> +			.hw.init	= CLK_HW_INIT_PARENTS(_name,	
\
> +							      
_parents, \
> +							      
&ccu_div_ops, \
> +							      
_flags),	\
> +			.features	= CCU_FEATURE_CLOSEST_RATE,	
\
> +		},						
	\
> +	}
> +
>  #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg,	\
>  				  _mshift, _mwidth, _muxshift, 
_muxwidth, \
>  				  _gate, _flags)		
	\
> @@ -152,6 +172,16 @@ struct ccu_div {
>  					_muxshift, _muxwidth,	
	\
>  					_gate, _flags)
> 
> +#define SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(_struct, _name, _parents,	
\
> +					  _reg, _mshift, 
_mwidth,	\
> +					  _muxshift, _muxwidth,	
	\
> +					  _gate, _flags)	
	\
> +	SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(_struct, _name,		
\
> +						_parents, 
NULL,		\
> +						_reg, 
_mshift, _mwidth,	\
> +						_muxshift, 
_muxwidth,	\
> +						_gate, 
_flags)
> +
>  #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg,		
\
>  			     _mshift, _mwidth, _muxshift, _muxwidth,	
\
>  			     _flags)				
	\




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