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Date: Mon, 7 Aug 2023 12:28:35 -0400
From: Alex Deucher <alexdeucher@...il.com>
To: Ran Sun <sunran001@...suo.com>
Cc: alexander.deucher@....com, airlied@...il.com, daniel@...ll.ch,
dri-devel@...ts.freedesktop.org, amd-gfx@...ts.freedesktop.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] drm/amd/pm: Clean up errors in vega10_powertune.c
Applied. Thanks!
On Mon, Jul 31, 2023 at 11:38 PM Ran Sun <sunran001@...suo.com> wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: that open brace { should be on the previous line
> ERROR: space prohibited after that open parenthesis '('
>
> Signed-off-by: Ran Sun <sunran001@...suo.com>
> ---
> .../amd/pm/powerplay/hwmgr/vega10_powertune.c | 89 +++++++------------
> 1 file changed, 31 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
> index 309a9d3bc1b7..3007b054c873 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
> @@ -30,8 +30,7 @@
> #include "pp_debug.h"
> #include "soc15_common.h"
>
> -static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -55,8 +54,7 @@ static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -120,8 +118,7 @@ static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -149,8 +146,7 @@ static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -172,8 +168,7 @@ static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] =
> };
>
>
> -static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -201,8 +196,7 @@ static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -260,8 +254,7 @@ static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] =
> };
>
>
> -static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -293,8 +286,7 @@ static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -362,8 +354,7 @@ static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SELCacConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SELCacConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -401,8 +392,7 @@ static const struct vega10_didt_config_reg SELCacConfig_Vega10[] =
> };
>
>
> -static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -431,8 +421,7 @@ static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -451,8 +440,7 @@ static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[]
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -478,8 +466,7 @@ static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -492,8 +479,7 @@ static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -514,8 +500,7 @@ static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -536,8 +521,7 @@ static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -571,8 +555,7 @@ static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg GCDiDtDroopCtrlConfig_vega10[] =
> -{
> +static const struct vega10_didt_config_reg GCDiDtDroopCtrlConfig_vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -586,8 +569,7 @@ static const struct vega10_didt_config_reg GCDiDtDroopCtrlConfig_vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg GCDiDtCtrl0Config_vega10[] =
> -{
> +static const struct vega10_didt_config_reg GCDiDtCtrl0Config_vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -601,8 +583,7 @@ static const struct vega10_didt_config_reg GCDiDtCtrl0Config_vega10[] =
> };
>
>
> -static const struct vega10_didt_config_reg PSMSEEDCStallPatternConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg PSMSEEDCStallPatternConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -621,8 +602,7 @@ static const struct vega10_didt_config_reg PSMSEEDCStallPatternConfig_Vega10[]
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg PSMSEEDCStallDelayConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg PSMSEEDCStallDelayConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -651,8 +631,7 @@ static const struct vega10_didt_config_reg PSMSEEDCStallDelayConfig_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg PSMSEEDCCtrlResetConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg PSMSEEDCCtrlResetConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -673,8 +652,7 @@ static const struct vega10_didt_config_reg PSMSEEDCCtrlResetConfig_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg PSMSEEDCCtrlConfig_Vega10[] =
> -{
> +static const struct vega10_didt_config_reg PSMSEEDCCtrlConfig_Vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -695,8 +673,7 @@ static const struct vega10_didt_config_reg PSMSEEDCCtrlConfig_Vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg PSMGCEDCDroopCtrlConfig_vega10[] =
> -{
> +static const struct vega10_didt_config_reg PSMGCEDCDroopCtrlConfig_vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -710,8 +687,7 @@ static const struct vega10_didt_config_reg PSMGCEDCDroopCtrlConfig_vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg PSMGCEDCCtrlResetConfig_vega10[] =
> -{
> +static const struct vega10_didt_config_reg PSMGCEDCCtrlResetConfig_vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -726,8 +702,7 @@ static const struct vega10_didt_config_reg PSMGCEDCCtrlResetConfig_vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg PSMGCEDCCtrlConfig_vega10[] =
> -{
> +static const struct vega10_didt_config_reg PSMGCEDCCtrlConfig_vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -742,8 +717,7 @@ static const struct vega10_didt_config_reg PSMGCEDCCtrlConfig_vega10[] =
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg AvfsPSMResetConfig_vega10[]=
> -{
> +static const struct vega10_didt_config_reg AvfsPSMResetConfig_vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -756,8 +730,7 @@ static const struct vega10_didt_config_reg AvfsPSMResetConfig_vega10[]=
> { 0xFFFFFFFF } /* End of list */
> };
>
> -static const struct vega10_didt_config_reg AvfsPSMInitConfig_vega10[] =
> -{
> +static const struct vega10_didt_config_reg AvfsPSMInitConfig_vega10[] = {
> /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> * Offset Mask Shift Value
> * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> @@ -919,7 +892,7 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
>
> mutex_lock(&adev->grbm_idx_mutex);
> for (count = 0; count < num_se; count++) {
> - data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
> + data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
> WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
>
> result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
> @@ -970,7 +943,7 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
>
> mutex_lock(&adev->grbm_idx_mutex);
> for (count = 0; count < num_se; count++) {
> - data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
> + data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
> WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
>
> result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
> @@ -1031,7 +1004,7 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
>
> mutex_lock(&adev->grbm_idx_mutex);
> for (count = 0; count < num_se; count++) {
> - data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
> + data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
> WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
> result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
> result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
> @@ -1081,7 +1054,7 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
>
> mutex_lock(&adev->grbm_idx_mutex);
> for (count = 0; count < num_se; count++) {
> - data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
> + data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
> WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
> result = vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
> result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
> --
> 2.17.1
>
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