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Message-ID: <CADnq5_O0O47XB0pbHFTX=afGcfa1LpD1rVVL4a+xbf1w8emEmA@mail.gmail.com>
Date: Mon, 7 Aug 2023 13:10:55 -0400
From: Alex Deucher <alexdeucher@...il.com>
To: Ran Sun <sunran001@...suo.com>
Cc: alexander.deucher@....com, dri-devel@...ts.freedesktop.org,
amd-gfx@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] drm/amd/display: Clean up errors in dcn315_smu.c
Applied. Thanks!
On Tue, Aug 1, 2023 at 10:58 PM Ran Sun <sunran001@...suo.com> wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: open brace '{' following struct go on the same line
> ERROR: code indent should use tabs where possible
>
> Signed-off-by: Ran Sun <sunran001@...suo.com>
> ---
> .../display/dc/clk_mgr/dcn315/dcn315_smu.c | 26 +++++++++----------
> 1 file changed, 12 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
> index 925d6e13620e..3e0da873cf4c 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
> @@ -33,28 +33,26 @@
> #define MAX_INSTANCE 6
> #define MAX_SEGMENT 6
>
> -struct IP_BASE_INSTANCE
> -{
> +struct IP_BASE_INSTANCE {
> unsigned int segment[MAX_SEGMENT];
> };
>
> -struct IP_BASE
> -{
> +struct IP_BASE {
> struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
> };
>
> static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
> - { { 0, 0, 0, 0, 0, 0 } },
> - { { 0, 0, 0, 0, 0, 0 } },
> - { { 0, 0, 0, 0, 0, 0 } },
> - { { 0, 0, 0, 0, 0, 0 } },
> - { { 0, 0, 0, 0, 0, 0 } } } };
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
> static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
> - { { 0, 0, 0, 0, 0, 0 } },
> - { { 0, 0, 0, 0, 0, 0 } },
> - { { 0, 0, 0, 0, 0, 0 } },
> - { { 0, 0, 0, 0, 0, 0 } },
> - { { 0, 0, 0, 0, 0, 0 } } } };
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0, 0 } } } };
>
> #define regBIF_BX_PF2_RSMU_INDEX 0x0000
> #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1
> --
> 2.17.1
>
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