linux-kernel - Re: [PATCH] drm/amdgpu: Clean up errors in uvd_v7

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Message-ID: <CADnq5_Ntw2+Ett+JVPtye1RH4yi8WBD3si7_CqfErvC9keUi1A@mail.gmail.com>
Date:   Mon, 7 Aug 2023 13:22:20 -0400
From:   Alex Deucher <alexdeucher@...il.com>
To:     Ran Sun <sunran001@...suo.com>
Cc:     alexander.deucher@....com, dri-devel@...ts.freedesktop.org,
        amd-gfx@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] drm/amdgpu: Clean up errors in uvd_v7_0.c

Applied.  Thanks!

On Wed, Aug 2, 2023 at 2:58 AM Ran Sun <sunran001@...suo.com> wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: spaces required around that ':' (ctx:VxE)
> that open brace { should be on the previous line
>
> Signed-off-by: Ran Sun <sunran001@...suo.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 7 +++----
>  1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index abaa4463e906..86d1d46e1e5e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -679,11 +679,11 @@ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
>                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
>                                 i == 0 ?
> -                               adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo:
> +                               adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo :
>                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo);
>                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
>                                 i == 0 ?
> -                               adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi:
> +                               adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi :
>                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi);
>                         WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
>                         offset = 0;
> @@ -1908,8 +1908,7 @@ static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
>         }
>  }
>
> -const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
> -{
> +const struct amdgpu_ip_block_version uvd_v7_0_ip_block = {
>                 .type = AMD_IP_BLOCK_TYPE_UVD,
>                 .major = 7,
>                 .minor = 0,
> --
> 2.17.1
>