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Message-ID: <CADnq5_MwqU2dumXc4tjkap63sv4ynni29M3=MTFngzmbZ0BbLw@mail.gmail.com>
Date: Mon, 7 Aug 2023 13:29:53 -0400
From: Alex Deucher <alexdeucher@...il.com>
To: Ran Sun <sunran001@...suo.com>
Cc: alexander.deucher@....com, dri-devel@...ts.freedesktop.org,
amd-gfx@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] drm/amdgpu: Clean up errors in nv.c
Applied. Thanks!
On Wed, Aug 2, 2023 at 3:34 AM Ran Sun <sunran001@...suo.com> wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: that open brace { should be on the previous line
>
> Signed-off-by: Ran Sun <sunran001@...suo.com>
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 48 +++++++++++----------------------
> 1 file changed, 16 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 51523b27a186..414c3c85172d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -67,21 +67,18 @@
> static const struct amd_ip_funcs nv_common_ip_funcs;
>
> /* Navi */
> -static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
> -{
> +static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = {
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
> };
>
> -static const struct amdgpu_video_codecs nv_video_codecs_encode =
> -{
> +static const struct amdgpu_video_codecs nv_video_codecs_encode = {
> .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
> .codec_array = nv_video_codecs_encode_array,
> };
>
> /* Navi1x */
> -static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
> -{
> +static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = {
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
> @@ -91,8 +88,7 @@ static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
> };
>
> -static const struct amdgpu_video_codecs nv_video_codecs_decode =
> -{
> +static const struct amdgpu_video_codecs nv_video_codecs_decode = {
> .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
> .codec_array = nv_video_codecs_decode_array,
> };
> @@ -108,8 +104,7 @@ static const struct amdgpu_video_codecs sc_video_codecs_encode = {
> .codec_array = sc_video_codecs_encode_array,
> };
>
> -static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] =
> -{
> +static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = {
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
> @@ -120,8 +115,7 @@ static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[]
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
> };
>
> -static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] =
> -{
> +static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = {
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
> @@ -131,27 +125,23 @@ static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[]
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
> };
>
> -static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 =
> -{
> +static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = {
> .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0),
> .codec_array = sc_video_codecs_decode_array_vcn0,
> };
>
> -static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 =
> -{
> +static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = {
> .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1),
> .codec_array = sc_video_codecs_decode_array_vcn1,
> };
>
> /* SRIOV Sienna Cichlid, not const since data is controlled by host */
> -static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
> -{
> +static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = {
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
> };
>
> -static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] =
> -{
> +static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = {
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
> @@ -162,8 +152,7 @@ static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[]
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
> };
>
> -static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] =
> -{
> +static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = {
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
> @@ -173,20 +162,17 @@ static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[]
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
> };
>
> -static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
> -{
> +static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = {
> .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
> .codec_array = sriov_sc_video_codecs_encode_array,
> };
>
> -static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 =
> -{
> +static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = {
> .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0),
> .codec_array = sriov_sc_video_codecs_decode_array_vcn0,
> };
>
> -static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 =
> -{
> +static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = {
> .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1),
> .codec_array = sriov_sc_video_codecs_decode_array_vcn1,
> };
> @@ -536,8 +522,7 @@ static void nv_program_aspm(struct amdgpu_device *adev)
>
> }
>
> -const struct amdgpu_ip_block_version nv_common_ip_block =
> -{
> +const struct amdgpu_ip_block_version nv_common_ip_block = {
> .type = AMD_IP_BLOCK_TYPE_COMMON,
> .major = 1,
> .minor = 0,
> @@ -642,8 +627,7 @@ static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
> return 0;
> }
>
> -static const struct amdgpu_asic_funcs nv_asic_funcs =
> -{
> +static const struct amdgpu_asic_funcs nv_asic_funcs = {
> .read_disabled_bios = &nv_read_disabled_bios,
> .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
> .read_register = &nv_read_register,
> --
> 2.17.1
>
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