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Message-Id: <20230807065942.9937-4-zhangqing@rock-chips.com>
Date: Mon, 7 Aug 2023 14:59:41 +0800
From: Elaine Zhang <zhangqing@...k-chips.com>
To: mturquette@...libre.com, sboyd@...nel.org,
kever.yang@...k-chips.com, zhangqing@...k-chips.com,
heiko@...ech.de, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org, linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org, huangtao@...k-chips.com
Subject: [RESEND PATCH v3 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id
add PCLK_VO1GRF clk id.
Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
---
include/dt-bindings/clock/rockchip,rk3588-cru.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h
index b5616bca7b44..864a321ab362 100644
--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
@@ -733,8 +733,9 @@
#define ACLK_AV1_PRE 718
#define PCLK_AV1_PRE 719
#define HCLK_SDIO_PRE 720
+#define PCLK_VO1GRF 721
-#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
+#define CLK_NR_CLKS (PCLK_VO1GRF + 1)
/* scmi-clocks indices */
--
2.17.1
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