linux-kernel - RE: [PATCH v2] clk: imx: composite-8m: fix clock pauses when set

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Message-ID: <DU0PR04MB941738BCFEB341B4DADA49AD880CA@DU0PR04MB9417.eurprd04.prod.outlook.com>
Date:   Mon, 7 Aug 2023 08:24:49 +0000
From:   Peng Fan <peng.fan@....com>
To:     Ahmad Fatoum <a.fatoum@...gutronix.de>,
        Abel Vesa <abelvesa@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        dl-linux-imx <linux-imx@....com>
CC:     "Peng Fan (OSS)" <peng.fan@....nxp.com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2] clk: imx: composite-8m: fix clock pauses when set_rate
 would be a no-op

> Subject: [PATCH v2] clk: imx: composite-8m: fix clock pauses when set_rate
> would be a no-op
> 
> Reconfiguring the clock divider to the exact same value is observed on an
> i.MX8MN to often cause a longer than usual clock pause, probably because
> the divider restarts counting whenever the register is rewritten.
> 
> This issue doesn't show up normally, because the clock framework will take
> care to not call set_rate when the clock rate is the same.
> However, when we reconfigure an upstream clock, the common code will
> call set_rate with the newly calculated rate on all children, e.g.:
> 
>   - sai5 is running normally and divides Audio PLL out by 16.
>   - Audio PLL rate is increased by 32Hz (glitch-free kdiv change)
>   - rates for children are recalculated and rates are set recursively
>   - imx8m_clk_composite_divider_set_rate(sai5) is called with
>     32/16 = 2Hz more
>   - imx8m_clk_composite_divider_set_rate computes same divider as before
>   - divider register is written, so it restarts counting from zero and
>     MCLK is briefly paused, so instead of e.g. 40ns, MCLK is low for 120ns.
> 
> Some external clock consumers can be upset by such unexpected clock
> pauses, so let's make sure we only rewrite the divider value when the value
> to be written is actually different.
> 
> Fixes: d3ff9728134e ("clk: imx: Add imx composite clock")
> Signed-off-by: Ahmad Fatoum <a.fatoum@...gutronix.de>

Reviewed-by: Peng Fan <peng.fan@....com>

Regards,
Peng.