linux-kernel - Re: [PATCH v3 11/12] x86/virt/tdx: Allow SEAMCALL to handle #UD and #GP

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <c4b1ab39b8e6e03e40ca390a41c96d096325428f.camel@intel.com>
Date:   Mon, 7 Aug 2023 12:41:13 +0000
From:   "Huang, Kai" <kai.huang@...el.com>
To:     "kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>
CC:     "Hansen, Dave" <dave.hansen@...el.com>,
        "Christopherson,, Sean" <seanjc@...gle.com>,
        "x86@...nel.org" <x86@...nel.org>, "bp@...en8.de" <bp@...en8.de>,
        "peterz@...radead.org" <peterz@...radead.org>,
        "hpa@...or.com" <hpa@...or.com>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "Yamahata, Isaku" <isaku.yamahata@...el.com>,
        "sathyanarayanan.kuppuswamy@...ux.intel.com" 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>,
        "n.borisov.lkml@...il.com" <n.borisov.lkml@...il.com>
Subject: Re: [PATCH v3 11/12] x86/virt/tdx: Allow SEAMCALL to handle #UD and
 #GP

On Mon, 2023-08-07 at 12:53 +0300, kirill.shutemov@...ux.intel.com wrote:
> On Mon, Aug 07, 2023 at 02:14:37AM +0000, Huang, Kai wrote:
> > On Sun, 2023-08-06 at 14:41 +0300, kirill.shutemov@...ux.intel.com wrote:
> > > On Wed, Jul 26, 2023 at 11:25:13PM +1200, Kai Huang wrote:
> > > > @@ -20,6 +21,9 @@
> > > >  #define TDX_SW_ERROR			(TDX_ERROR | GENMASK_ULL(47, 40))
> > > >  #define TDX_SEAMCALL_VMFAILINVALID	(TDX_SW_ERROR | _UL(0xFFFF0000))
> > > >  
> > > > +#define TDX_SEAMCALL_GP			(TDX_SW_ERROR | X86_TRAP_GP)
> > > > +#define TDX_SEAMCALL_UD			(TDX_SW_ERROR | X86_TRAP_UD)
> > > 
> > > Is there any explantion how these error codes got chosen? Looks very
> > > arbitrary and may collide with other error codes in the future.
> > > 
> > 
> > Any error code has TDX_SW_ERROR is reserved to software use so the TDX module
> > can never return any error code which conflicts with those software ones.
> > 
> > For why to choose these two, I believe XOR the TRAP number to TDX_SW_ERROR is
> > the simplest way to achieve: 1) costing minimal assembly code; 2)
> > opportunistically handling #GP too, allowing caller to distinguish the two
> > errors.
> 
> My problem is that it is going to conflict with errno-based errors if we
> going to take this path in the future. Like these errors are the same as
> (TDX_SW_ERROR | EACCES) and (TDX_SW_ERROR | ENXIO) respectively.
> 

Is there any use case that we need those definitions?

Even we have such requirement in the future, we still have many bits available
after taking out the bits of TDX_SW_ERROR thus I assume we can do some bit shift
when this really happens??