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Message-ID: <ZNDvVlbubtOoto0p@andrea>
Date: Mon, 7 Aug 2023 15:19:18 +0200
From: Andrea Parri <parri.andrea@...il.com>
To: Mathieu Desnoyers <mathieu.desnoyers@...icios.com>
Cc: paulmck@...nel.org, paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, mmaas@...gle.com, hboehm@...gle.com,
striker@...ibm.com
Subject: Re: [RFC PATCH] membarrier: riscv: Provide core serializing command
> One more noteworthy detail: if a system call similar to ARM cacheflush(2) is implemented for
> RISC-V, perhaps an iovec ABI (similar to readv(2)/writev(2)) would be relevant to handle
> batching of cache flushing when address ranges are not contiguous. Maybe with a new name
> like "cacheflushv(2)", so eventually other architectures could implement it as well ?
I believe that's a sensible idea. But the RISC-V maintainers can provide
a more reliable feedback.
Andrea
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