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Date: Mon, 7 Aug 2023 20:22:19 -0700
From: Dan Williams <dan.j.williams@...el.com>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@....com>,
Sathyanarayanan Kuppuswamy
<sathyanarayanan.kuppuswamy@...ux.intel.com>,
<linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-cxl@...r.kernel.org>
CC: Bjorn Helgaas <bhelgaas@...gle.com>, <oohall@...il.com>,
Lukas Wunner <lukas@...ner.de>,
Mahesh J Salgaonkar <mahesh@...ux.ibm.com>,
"Alison Schofield" <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
Ira Weiny <ira.weiny@...el.com>,
Ben Widawsky <bwidawsk@...nel.org>,
Dan Williams <dan.j.williams@...el.com>,
"Jonathan Cameron" <Jonathan.Cameron@...wei.com>,
Yazen Ghannam <yazen.ghannam@....com>,
Terry Bowman <terry.bowman@....com>,
Robert Richter <rrichter@....com>
Subject: Re: [PATCH v2 1/3] cxl/pci: Fix appropriate checking for _OSC while
handling CXL RAS registers
Smita Koralahalli wrote:
>
> >> - /* BIOS has CXL error control */
> >> - if (!host_bridge->native_cxl_error)
> >> - return -ENXIO;
> >> + /* BIOS has PCIe AER error control */
> >> + if (!host_bridge->native_aer)
> >> + return 0;
> >
> > Why not directly use pcie_aer_is_native() here?
> Yeah, this was in my v1. But changed as per Robert's comments, to be
> applicable for automated backports..
>
> https://lore.kernel.org/all/ZLkxiZv3lWfazwVH@rric.localdomain/
>
> Please advice.
Keep it the way you have it. Minimizing the backport is the right call.
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